Because FPGAs operate differently than standard PC processors, you need to keep in mind different considerations when you create a VI to run on an FPGA target versus when you create a VI to run on a PC. The following palettes contain objects with FPGA-specific considerations.

The channel wire endpoints also have FPGA-specific considerations.

The details for each object include a table with the following FPGA-specific considerations.

  • Single-Cycle Timed Loop—Specifies whether you can use the VI or function inside a single-cycle Timed Loop.
  • Usage—Contains information about the behavior of the VI or function when used in an FPGA VI.
  • Timing—Contains information about the amount of time the VI or function takes to execute. Inside the single-cycle Timed Loop, this information refers to the combinatorial path length of the VI or function. Outside the single-cycle Timed Loop, this information refers to the number of clock cycles a VI or function takes to execute.
  • Properties Dialog Box—Contains information about the behavior of the VI or function when you enable the Adapt to source checkbox in the Properties dialog box.
  • Resources—Contains information about the FPGA resource usage of the VI or function.
  • Notes—Contains additional useful information that you can refer to when using the VI or function.