This topic contains FPGA-specific information about the objects on the Array Functions palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.
array constant
Single-Cycle Timed Loop Supported.
Usage You can view the memory implementation for an array constant in the Context Help window when you hover over an array constant. To select a memory implementation, right-click an array and select Properties. Select Auto, Flip Flops, Look-Up Tables, or Block Memory on the FPGA Implementation tab of the Array Constant Properties dialog box.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function alone consumes no FPGA resources. However, when the array constant is wired to a logic operation, the array uses FPGA lookup table resources, except when implemented in block memory. Large arrays can be time and resource intensive if you perform logical operations on each element of the array. Avoid using arrays larger than 32 elements with 16-bit data unless you choose a block memory or look-up table implementation for array constants.
Array Size
Single-Cycle Timed Loop Supported.
Usage N/A
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Array Subset
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The index and length inputs must be constant so that LabVIEW can determine the size of subarray. You can either wire constant values directly to this function, or rely on value propagation through constant folding.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Array To Cluster
Single-Cycle Timed Loop Supported.
Usage N/A
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Build Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. If LabVIEW cannot infer a single size for an array, you may need to manually configure the array to a fixed size.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Cluster To Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. If LabVIEW cannot infer a single size for an array, you may need to manually configure the array to a fixed size.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Decimate 1D Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. You can use constant or non-constant inputs.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Delete From Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The index and length inputs must be constant so that LabVIEW can determine the size of array w/ subset deleted and deleted portion. You can either wire constant values directly to this function, or rely on value propagation through constant folding.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Index Array
Single-Cycle Timed Loop Supported.
Usage N/A
Timing This function executes in one clock cycle, unless you wire a constant immediately into the index input, in which case the selection occurs at compile time and the function requires no clock cycles.
Resources When the index is not constant, this function consumes FPGA resources in proportion to the size of the array and size of the element. When the index is constant, this function consumes no FPGA resources.
Notes For large arrays, the Index Array function might not be able to execute within a single clock cycle, resulting in a compile-time error.
Initialize Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The dimension size input must be constant so that LabVIEW can determine the size of the output array. You can either wire constant values directly to this function, or rely on value propagation through constant folding. If LabVIEW cannot infer a single size for an array, you may need to manually configure the array to a fixed size.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Notes Although the size of the array you initialize does not affect the timing and resource usage of this function, large arrays can be time and resource intensive when you perform logical operations on the elements of the array.
Insert Into Array
Single-Cycle Timed Loop Supported.
Usage If the index input is beyond the range of the array into which you are inserting elements, this function does not insert anything into the input array. The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The index input must be constant so that LabVIEW can determine the size of the output array. You can either wire constant values directly to this function, or rely on value propagation through constant folding.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Interleave 1D Arrays
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. You can use constant or non-constant inputs.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Replace Array Subset
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. You can use constant or non-constant inputs.
Timing This function executes in one clock cycle. However, if you wire a constant immediately into the index input, the selection occurs at compile time and the function requires no clock cycles.
Resources When the index is not constant, this function consumes FPGA resources in proportion to the size of the array and size of new element/subarray. When the index is constant, this function consumes no FPGA resources.
Notes For large arrays, the Replace Array Subset function might not be able to execute within a single clock cycle, resulting in a compile-time error.
Reshape Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The dimension size input must be constant so that LabVIEW can determine the size of the output array. You can either wire constant values directly to this function, or rely on value propagation through constant folding.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Reverse 1D Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. You can use constant or non-constant inputs.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Rotate 1D Array
Single-Cycle Timed Loop Not Supported.
Usage If you wire a constant directly to the n input, this function is purely a wiring operation. Otherwise, this function implements an iterative algorithm, rotating the elements by one position each clock cycle.
Timing If n is a constant, this operation requires no clock cycles. Otherwise, this operation takes n clock cycles to execute, plus three clock cycles of overhead.
Resources If you wire a constant directly to the n input, this operation consumes no FPGA resources. Otherwise, this operation consumes FPGA resources in proportion to the size of the array.
Split 1D Array
Single-Cycle Timed Loop Supported.
Usage The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The index input must be constant so that LabVIEW can determine the size of the output array. You can either wire constant values directly to this function, or rely on value propagation through constant folding.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.