Conversion Palette Details (FPGA Module)
- Updated2025-01-28
- 3 minute(s) read
This topic contains FPGA-specific information about the objects on the Conversion Functions palette.
The following details apply to all the Conversion functions, except the Boolean Array to Number, Number To Boolean Array, To Fixed-Point, and To Single Precision Float functions.
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | The Conversion functions require no clock cycles to execute because they do not include internal registers. If you use the Conversion functions with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | The Conversion functions consume no FPGA resources because they are purely wiring operations. If you use the Conversion functions with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | The FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. The Boolean Array To Number function converts fixed-size arrays by default to use the smallest unsigned integer representation that will fit the array size. |
| Timing | This function requires no clock cycles to execute because it does not include internal registers. |
| Properties Dialog Box | The data type of number changes based on the size of the array when the Adapt to source checkbox in the Output Configuration page contains a checkmark. The following list describes the relationship between the array size and the data type of number:
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| Resources | This function consumes no FPGA resources because it is purely a wiring operation. |
| Single-Cycle Timed Loop | Supported. |
| Usage | The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. If LabVIEW cannot infer a single size for an array, you may need to manually configure the array to a fixed size. You cannot wire an array or cluster to this function. |
| Timing | This function requires no clock cycles to execute because it does not include an internal register. |
| Resources | This function consumes no FPGA resources because it is purely a wiring operation. |
| Single-Cycle Timed Loop | Supported for fixed-point and integer inputs only. |
| Usage | This function does not support array inputs. However, you can pass array data to this function element-by-element if you meet the following criteria:
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| Timing | This function requires no clock cycles for fixed-point and integer inputs if you select the Wrap overflow mode and Truncate rounding mode. Other overflow and rounding modes might impact timing. This function requires multiple cycles to execute for single-precision floating-point inputs. |
| Resources | This function consumes no FPGA resources for fixed-point and integer inputs if you select the Wrap overflow mode and Truncate rounding mode. Other overflow and rounding modes might impact resources. This function consumes significant FPGA resources when the input type is single-precision floating-point in order to scale the significand to the appropriate output type. |
| Notes | You also can use the High Throughput To Fixed-Point function to perform fixed-point math and analysis on an FPGA target. |
| Single-Cycle Timed Loop | Not supported. |
| Usage | N/A |
| Timing | This function requires multiple cycles to execute for all input types. |
| Resources | This function consumes significant FPGA resources in order to normalize fixed-point or integer values and compute their exponents. Resource usage is roughly proportional to the width of the input fixed-point or integer value. |