Reducing Combinatorial Paths in FPGA VIs
- Updated2025-09-18
- 1 minute(s) read
Long combinatorial paths take more time to execute and limit the maximum clock rate of the clock domain.
Long combinatorial paths are typically a problem in single-cycle Timed Loops because the logic between the input register and the output register must execute within one period of the clock rate you specify. In the single-cycle Timed Loop, LabVIEW removes registers within and between components, which increases the length of the combinatorial path between registers. If the code in a combinatorial path cannot execute within a clock cycle, LabVIEW returns a timing violation in the Compilation Status window.
To reduce the length of a combinatorial path, first simplify the logic as much as possible. Once you have reduced the logic to its simplest form, you can further reduce the length of a combinatorial path by dividing the logic into discrete steps and pipelining your design.