This topic contains detailed information about the objects on the Data Manipulation Functions palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.
Join Numbers
Single-Cycle Timed Loop Supported.
Usage N/A
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Logical Shift
Single-Cycle Timed Loop Supported.
Usage The logical shift operation shifts all bits including the sign bit of a signed integer. To preserve the sign of a signed integer, use the Scale By Power Of 2 function.
Timing

Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x.

Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.

Resources This function requires FPGA resources proportional to the number of bits in x.
Rotate
Single-Cycle Timed Loop Supported.
Usage N/A
Timing

Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x.

Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.

Resources This function requires FPGA resources proportional to the number of bits in x.
Rotate Left With Carry
Single-Cycle Timed Loop Supported.
Usage You cannot wire an array or cluster input to this function in a single-cycle Timed Loop.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Rotate Right With Carry
Single-Cycle Timed Loop Supported.
Usage You cannot wire an array or cluster input to this function in a single-cycle Timed Loop.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Split Number
Single-Cycle Timed Loop Supported.
Usage This function supports array and cluster inputs of all data types except fixed-point.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Swap Bytes
Single-Cycle Timed Loop Supported.
Usage You cannot wire a fixed-point data type to this function.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
Swap Words
Single-Cycle Timed Loop Supported.
Usage You cannot wire a fixed-point data type to this function.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.