This topic contains FPGA-specific information about the objects on the Comparison Functions palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

The following details apply to all the Comparison functions, except for the Fixed Point Overflow?, In Range and Coerce, Max & Min, and Not A Number/Path/Refnum? functions.

Single-Cycle Timed Loop Supported.
Usage If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.
Timing

Inside single-cycle Timed Loop--When you use Comparison functions inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the width of the data types you compare.

Outside single-cycle Timed Loop--When you use Comparison functions outside a single-cycle Timed Loop, each Comparison function takes one clock cycle.

If you use the Comparison functions with the fixed-point data type, the overflow and rounding modes might impact timing.

Resources The Comparison functions use FPGA resources in proportion to the width of the data types you compare.
Fixed-Point Overflow?
Single-Cycle Timed Loop Supported.
Usage N/A
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.
In Range and Coerce
Single-Cycle Timed Loop Supported.
Usage

If the value of lower limit is greater than the value of upper limit, LabVIEW does not swap the values of lower limit and upper limit. You must change the values of lower limit and upper limit manually if you do not want the value of lower limit to be greater than the value of upper limit.

You cannot wire an array or cluster to this function in a single-cycle Timed Loop.

If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.
Timing

Inside single-cycle Timed Loop--When you use Comparison functions inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the width of the data types you compare.

Outside single-cycle Timed Loop--When you use Comparison functions outside a single-cycle Timed Loop, each Comparison function takes one clock cycle.

If you use the Comparison functions with the fixed-point data type, the overflow and rounding modes might impact timing.

Resources The Comparison functions use FPGA resources in proportion to the width of the data types you compare.
Max & Min
Single-Cycle Timed Loop Supported.
Usage

This function does not support Compare Aggregates mode.

If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.
Timing

Inside single-cycle Timed Loop--When you use Comparison functions inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the width of the data types you compare.

Outside single-cycle Timed Loop--When you use Comparison functions outside a single-cycle Timed Loop, each Comparison function takes one clock cycle.

Resources The Comparison functions use FPGA resources in proportion to the width of the data types you compare.
Not A Number/Path/Refnum?
Single-Cycle Timed Loop Supported.
Usage The FPGA Module supports only the Not A Number functionality.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes FPGA resources only when the input is single-precision floating-point (SGL). When the input is anything other than a SGL, the function returns a FALSE constant and is optimized out if not connected to other logic.