This topic contains FPGA-specific information about the objects on the Assert Type palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.
Assert Structural Type Match
Single-Cycle Timed Loop Supported.
Usage This function does nothing at run time. It breaks the calling VI unless the two input data types are identical.
Timing This function requires no clock cycles to execute because it does nothing at run time.
Resources This function consumes no FPGA resources because it does nothing at run time.
Assert Structural Type Mismatch
Single-Cycle Timed Loop Supported.
Usage This function does nothing at run time. It breaks the calling VI if the input type is the same data type as any of the specified mismatch inputs.
Timing This function requires no clock cycles to execute because it does nothing at run time.
Resources This function consumes no FPGA resources because it does nothing at run time.
Type Specialization Structure
Single-Cycle Timed Loop Supported.
Usage When you use the Type Specialization structure in an FPGA VI, LabVIEW evaluates the compilation results at compile time and compiles only one subdiagram.
Timing Entering and exiting this structure requires no time on the FPGA.
Resources Only one subdiagram of the Type Specialization structure compiles to the FPGA. Inactive subdiagrams consume no FPGA resources. The Type Specialization structure itself also consumes no FPGA resources.