This topic contains FPGA-specific information about the objects on the Boolean Functions palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

The following details apply to all the Boolean functions, except the Compound Arithmetic function, Number To Boolean Array function, and True and False constants.

Single-Cycle Timed Loop Supported.
Usage For maximum time and resource efficiency, use Boolean functions inside a single-cycle Timed Loop.
Timing

Inside single-cycle Timed Loop--When you use Boolean functions inside a single-cycle Timed Loop, each Boolean operation adds slightly to the combinatorial logic delay of the single-cycle Timed Loop.

Outside single-cycle Timed Loop--When you use Boolean functions outside a single-cycle Timed Loop, each Boolean operation requires one clock cycle.

Resources Boolean functions consume significant FPGA resources only when you wire a large array to the input. Consider limiting arrays to conserve FPGA resources.
Compound Arithmetic
Single-Cycle Timed Loop Supported.
Usage

If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.

When used in an FPGA VI, the Compound Arithmetic function might return different results for floating-point operations, as this function executes operations in a different order than when used on a host computer.
Timing When placed inside a single-cycle Timed Loop, the combinatorial logic delay is logarithmically proportional to the number of inputs.
Resources This function consumes FPGA resources in proportion to the number of inputs, N. Each operation receives dedicated hardware and the total number of operations is always N - 1.
Number To Boolean Array
Single-Cycle Timed Loop Supported.
Usage

The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. If LabVIEW cannot infer a single size for an array, you may need to manually configure the array to a fixed size.

You cannot wire an array or cluster to this function.
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function consumes no FPGA resources because it is purely a wiring operation.

True and False Constants

The following details apply to the True constant and the False constant.

Single-Cycle Timed Loop Supported.
Usage N/A
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This function alone consumes no FPGA resources. However, when you wire a True or False constant to a logical operation, the value is combined with the logical operation.