Numeric Palette Details (FPGA Module)
- Updated2025-01-28
- 12 minute(s) read
This topic contains detailed information about the objects on the Numeric Functions palette.
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x or y, whichever data type is larger. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. When used in an FPGA VI, the Compound Arithmetic function might return different results for floating-point operations, as this function executes operations in a different order than when used on a host computer. |
| Timing | When placed inside a single-cycle Timed Loop, the combinatorial logic delay is logarithmically proportional to the number of inputs. |
| Resources | This function consumes FPGA resources in proportion to the number of inputs, N. Each operation receives dedicated hardware and the total number of operations is always N - 1. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Not supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | This function usually requires clock cycles in proportion to the number of bits in x/y. If you use this function with the fixed-point data type and select the Round-Half-Up rounding mode, the function requires one more clock cycle than the other two rounding modes. |
| Resources | Division is an expensive operation on the FPGA. In general, the function requires FPGA resources proportional to the number of bits in x, y, and x/y. If you use this function with the fixed-point data type, the rounding mode might impact resources. |
| Notes | You also can use the High Throughput Divide function to perform fixed-point math and analysis on an FPGA target. |
| Single-Cycle Timed Loop | Supported. |
| Usage | N/A |
| Timing | This function requires no clock cycles to execute and never includes an internal register. |
| Resources | This function alone consumes no FPGA resources. However, when you wire the constant to a logical operation, the constant uses FPGA lookup table resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
Machine Epsilon, Negative Infinity, and Positive Infinity
The following details apply to Machine Epsilon, Negative Infinity, and Positive Infinity
| Single-Cycle Timed Loop | Supported. |
| Usage | The default data type for these constants is single-precision floating-point (SGL). |
| Timing | These constants require no clock cycles to execute because they do not include internal registers. |
| Resources | These constants alone consume no FPGA resources. However, if you wire one of these constants to a logical operation, FPGA lookup table resources store the constant value. |
| Single-Cycle Timed Loop | Supported. |
| Usage | Most FPGA targets contain a limited number of embedded multipliers. The FPGA Module compiler uses embedded multipliers to implement multiply operations until it occupies all the embedded multipliers. If the FPGA target runs out of embedded multipliers, the compiler uses generic logic gates instead, and the Multiply function becomes expensive in terms of FPGA resource usage. If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x or y, whichever data type is larger. Consider using the smallest data type possible to optimize FPGA VIs. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Notes | You also can use the High Throughput Multiply function to perform fixed-point math and analysis on an FPGA target. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | N/A |
| Timing | This function requires no clock cycles to execute because it does not include an internal register. |
| Resources | This function alone consumes no FPGA resources. However, if you wire a Numeric constant to a logical operation, FPGA lookup table resources store the constant value. |
| Single-Cycle Timed Loop | Not supported. |
| Usage | Division is a relatively expensive operation on the FPGA in terms of both resource usage and time. Use the Scale By Power of 2 function with n wired as a negative constant to increase efficiency when dividing by a power of two. This function does not support the single-precision floating-point data type. |
| Timing | This function requires clock cycles and registers in proportion to the number of bits in x or y, whichever data type is larger. Each clock cycle corresponds to one register. |
| Resources | This function requires FPGA resources proportional to the number of bits in x or y, whichever data type is larger. |
| Single-Cycle Timed Loop | Not supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | This function normally requires clock cycles in proportion to the number of bits in 1/x. If you use this function with the fixed-point data type and select the Round-Half-Up rounding mode, the function requires one more clock cycle than the other two rounding modes. |
| Resources | Division is an expensive operation on the FPGA. In general, the function requires FPGA resources proportional to the number of bits in x and 1/x. If you use this function with the fixed-point data type, the rounding mode might impact resources. |
| Notes | You also can use the High Throughput Reciprocal function to perform fixed-point math and analysis on an FPGA target. |
| Single-Cycle Timed Loop | Supported. |
| Usage | N/A |
| Timing | This function requires no clock cycles to execute because it does not include an internal register. |
| Resources | This function alone consumes no FPGA resources because it is purely a wiring operation. |
| Single-Cycle Timed Loop | Supported. |
| Usage | This function does not support the single-precision floating-point data type. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. The overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. The overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | This function does not support the single-precision floating-point data type. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. The overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. The overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | This function does not support the single-precision floating-point data type. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in number. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. The overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in number. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you wire a constant directly to the n input, this function uses no space on the FPGA and requires no clock cycles. If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--If n is not a constant and you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--If n is not a constant and you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. |
| Resources | If n is not a constant, this function requires FPGA resources in proportion to the number of bits in x. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in number. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in number. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Supported. |
| Usage | Most FPGA targets contain a limited number of embedded multipliers. The FPGA Module compiler uses embedded multipliers to implement multiply operations until it occupies all the embedded multipliers. If the FPGA target runs out of embedded multipliers, the compiler uses generic logic gates instead, and the Square function becomes expensive in terms of FPGA resource usage. If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x. Consider using the smallest data type possible to optimize FPGA VIs. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Single-Cycle Timed Loop | Not supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | If the fractional word length of sqrt(x) is larger than half of the fractional word length of x, the function requires clock cycles in proportion to the number of bits in sqrt(x). Otherwise, the required clock cycles are proportional to the number of bits in x. |
| Resources | In general, the function requires FPGA resources proportional to the number of bits in x and sqrt(x). If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |
| Notes | You also can use the High Throughput Square Root function to perform fixed-point math and analysis on an FPGA target. |
| Single-Cycle Timed Loop | Supported. |
| Usage | If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications. |
| Timing | Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger. Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | This function requires FPGA resources proportional to the number of bits in x or y, whichever data type is larger. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources. |