This topic contains detailed information about the objects on the Structures palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.
Case Structure
Single-Cycle Timed Loop Supported.
Usage N/A
Timing

Inside single-cycle Timed Loop--When you use a Case structure inside a single-cycle Timed Loop, the combinatorial logic delay required to evaluate the case selector is proportional to the width of the selector input data type and the number of cases. The combinatorial logic delay introduced by output tunnels is proportional to the number of cases.

Outside single-cycle Timed Loop--When you use a Case structure outside a single-cycle Timed Loop, it takes one clock cycle to evaluate the case selector. Output tunnels require no clock cycles to execute and never include a register.

Resources The case selector requires FPGA resources proportional to the width of the input data type and the number of cases. Output tunnels require FPGA resources proportional to the width of the output data type and the number of cases.
Notes Complex Case structures can lead to long combinatorial paths and limit the maximum clock rate of a clock domain.
Conditional Disable Structure
Single-Cycle Timed Loop Supported.
Usage When you use the Conditional Disable structure in an FPGA VI, LabVIEW evaluates the conditions at compile time and compiles only one subdiagram.
Timing Entering and exiting this structure requires no time on the FPGA.
Resources Only one subdiagram of the Diagram Disable structure compiles to the FPGA. Inactive subdiagrams consume no FPGA resources. The Diagram Disable structure itself also consumes no FPGA resources.
Diagram Disable Structure
Single-Cycle Timed Loop Supported.
Usage When you use the Diagram Disable structure in an FPGA VI, front panel objects inside the structure do compile.
Timing Because the objects inside the Diagram Disable structure do not compile on the FPGA, this structure takes no time to execute.
Resources Each front panel object in a Diagram Disable structure consumes FPGA resources. Arrays controls appearing as top-level front panel objects consume significant space on the FPGA because each bit in the array uses a flip-flop on the FPGA. Consider replacing array controls with FIFOs or memory items to transfer data.
Feedback Node
Single-Cycle Timed Loop Supported.
Usage

You can use the Feedback Node to implement a pipeline and reduce long combinatorial paths. You also can use the Feedback Node for feedback in a subVI within a single-cycle Timed Loop. When you use the Feedback Node inside a Case structure, the Feedback Node updates data only on clock cycles when the owning subdiagram executes.

Right-click the Feedback Node and select Properties from the shortcut menu to open the Properties dialog box. On the Configuration page, you can specify more options for the Feedback Node.
Timing

Inside single-cycle Timed Loop--When you initialize a Feedback Node inside a single-cycle Timed Loop, initialization requires no clock cycles. However, if the initialized data comes from a different clock domain, initialization can take multiple clock cycles.

Outside single-cycle Timed Loop--Initialization of all Feedback Nodes outside the single-cycle Timed Loop requires one clock cycle.
Resources The Feedback Node is implemented as a register and requires FPGA resources in proportion to the width of the data type. Using the initialization terminal slightly increases FPGA resource usage.
Notes Consider using the Discrete Delay function instead of the Feedback Node.
Flat Sequence Structure
Single-Cycle Timed Loop Using a sequence structure inside a single-cycle Timed Loop has no sequencing effect.
Usage N/A
Timing This structure requires no clock cycles to execute because it does not include an internal register.
Resources This structure consumes minimal FPGA resources.
For Loop
Single-Cycle Timed Loop

Limited support.

You can place a For Loop in a single-cycle Timed Loop if the For Loop contains only Array, Numeric, Boolean, or Comparison operations and uses only auto-indexed tunnels. Objects that generate or contain state, such as shift registers, Feedback Nodes, or VI calls, are not allowed in For Loops within a single-cycle Timed Loop.
Usage

The iteration (i) terminal is a 32-bit signed integer that saturates on reaching its maximum value, 2^31 - 1.

The conditional terminal is not supported. Parallel loop iteration is not supported.
Timing The For Loop incurs two clock cycles of overhead between iterations. If the For Loop contains initialized shift registers, it takes one clock cycle before the first iteration to initialize shift register values.
Resources The For Loop consists of a small state machine. Shift registers require FPGA resources in proportion to the width of the data type. Loop auto-indexers consist of a hidden shift register for each array element.
Notes The LabVIEW FPGA Module supports only one-dimensional arrays that resolve to a single size at compile time. If LabVIEW cannot infer a single size for an array, you may need to manually configure the array to a fixed size.
Global Variable
Single-Cycle Timed Loop Supported.
Usage Global variables use less space on the FPGA than local variables, which makes them a better choice for data you do not need to transfer to a host VI.
Timing A global variable takes at least one clock cycle, whereas a wire takes no clock cycles. For maximum efficiency, avoid using a variable when a wire would suffice.
Resources A global variable consumes FPGA resources in proportion to the width of the data type.
Local Variable
Single-Cycle Timed Loop Supported.
Usage Global variables use less space on the FPGA than local variables, which makes them a better choice for data you do not need to transfer to a host VI.
Timing A local variable takes at least one clock cycle, whereas a wire takes no clock cycles. For maximum efficiency, avoid using a variable when a wire would suffice.
Resources A local variable consumes FPGA resources in proportion to the width of the data type, plus additional overhead to facilitate communication with a host VI. Consider limiting front panel objects, including those used as local variables, to optimize the FPGA VI.
Stacked Sequence Structure
Single-Cycle Timed Loop Using a sequence structure inside a single-cycle Timed Loop has no sequencing effect.
Usage N/A
Timing This function requires no clock cycles to execute because it does not include an internal register.
Resources This structure consumes minimal FPGA resources.
Timed Loop

Refer to the single-cycle Timed Loop topic for more information about using and configuring the Timed Loop in an FPGA VI.

Type Specialization Structure
Single-Cycle Timed Loop Supported.
Usage When you use the Type Specialization structure in an FPGA VI, LabVIEW evaluates the compilation results at compile time and compiles only one subdiagram.
Timing Entering and exiting this structure requires no time on the FPGA.
Resources Only one subdiagram of the Type Specialization structure compiles to the FPGA. Inactive subdiagrams consume no FPGA resources. The Type Specialization structure itself also consumes no FPGA resources.
While Loop
Single-Cycle Timed Loop Not supported.
Usage The iteration (i) terminal is a 32-bit signed integer that saturates on reaching its maximum value, 2^31 - 1.
Timing The While Loop incurs two clock cycles of overhead between iterations. If the While Loop contains initialized shift registers, it takes one clock cycle before the first iteration to initialize shift register values. Code placed in a While Loop generally takes longer to execute than the same code placed in a single-cycle Timed Loop.
Resources The While Loop consists of a small state machine. Shift registers require FPGA resources in proportion to the width of the data type. Loop auto-indexers consist of a hidden shift register for each array element.