To effectively simulate an FPGA design using the FPGA Desktop Execution Node, you must understand two time paradigms, real-world time and simulated time.
Real-world time is the physical amount of time that elapses while something occurs. Because an FPGA is a programmable circuit, it takes a fixed amount of real-world time to execute such a circuit.
To simulate a design, you can create a model that reflects the functional behavior of the FPGA and execute this model on a computer processor. However, such a model does not have the same real-world timing as the FPGA. To create a model that has the same real-world timing as the FPGA, you must use simulated time.
Simulated time is an event-driven model of real-world time. When LabVIEW executes block diagram nodes, the execution causes simulated time to advance a certain number of steps. Clock ticks are the unit of simulated time where one clock tick is representative of a single cycle of the referenced FPGA clock.
What Nodes Advance Simulated Time?
Not all nodes on the FPGA block diagram advance simulated time. Table 1 shows the block diagram nodes that advance simulated time and the simulation time step they register.
Table 1. Block Diagram Nodes that Advance Simulated Time
|Block Diagram Node||Time Step1|
|While Loop||Diagram execution time plus two ticks2|
|Single-Cycle Timed Loop||1 tick of the configured loop clock|
|Wait Express VI||User specified (ms, us, or ticks)|
|Loop Timer Express VI||User specified (ms, us, or ticks)3|
|FIFOs (except DMA)||User specified (ticks)|
|Wait on Occurrence VI||User specified (ms or ticks)|
|Interrupt VI4||One tick repeated until the interrupt is cleared|
1All time step behavior is relative to the top-level clock unless otherwise noted.
2The time step behavior of the While Loop is subject to change with each version of LabVIEW.
3The Loop Timer Express VI registers for the difference between the user-specified time step and the loop execution time step
4This only applies when you set the Wait Until Cleared input of the Interrupt VI to TRUE
Calculating Simulated Time
To fully understand how different parts of your LabVIEW FPGA code will interact with one another in simulation mode, you must calculate their impact on simulated time.
Using the details in table 1, you can manually inspect and calculate the simulated time step for a block diagram. Figure 1 shows an example VI that uses a 40 MHz top-level clock.
Figure 1. Example FPGA VI (40 MHz Top-Level Clock)
The following list describes important details about Figure 1.
A. The Loop Timer Express VI registers for a time step of 200 us, which is 8,000 ticks of the top-level clock, minus the time step of the rest of the While Loop.
B. The analog input, which is an FPGA input, does not register for any time step in simulation mode. FPGA output has the same behavior.
C. The Butterworth Filter Express VI contains a 40 MHz single-cycle timed loop that iterates once per call. Therefore, this express VI registers for a time step of 1 tick.
D. The target-scoped FIFO only registers for a time step of 1,000 ticks if the FIFO is timed out. Otherwise, no time step is registered.
E. Basic block diagram nodes including logic and math functions do not register for a simulation time step.
F. The While Loop registers for a time step of two ticks of the top-level clock.
Considering that manually calculating the simulated time step of a block of code is not always practical or necessary, you can calculate the simulated time step by using the Tick Count Express VI to benchmark the simulation execution time. Figure 2 shows the previous example VI instrumented to calculate the entire loop time step.
Figure 2. Example FPGA VI With Time Step Counter
The example VIs shown in Figure 1 and Figure 2 always execute with a simulated time step of 8,000 ticks, which equals 200 us, yielding a loop rate of 5 kHz. The Loop Timer Express VI applies a variable time step to enforce consistent timing between loop iterations, as shown in Table 2.
Table 2. Comparing Time Steps
| ||Time Step|
|Loop and Diagram||Loop Timer Express VI|
|When Timed Out? of the FIFO Write method returns FALSE||3 Ticks||7,997 Ticks|
|When Timed Out? of the FIFO Write method returns TRUE||1,003 Ticks||6,997 Ticks|
Enforcing Accurate Simulated Time
In real-world time (FPGA execution mode), every node on the FPGA block diagram is represented by some physical circuitry and takes time to execute. In simulated time (FPGA simulation mode), only some nodes advance time. Because of this difference in the time paradigms, you must properly enforce simulated timing so the simulation behaves like FPGA execution. Figure 3 shows an example without properly enforced simulated timing.
Figure 3. Example Without Proper Enforcement of Simulated Time
The example in Figure 3 contains two independent loops, which both run on the 40 MHz top-level clock. Table 3 analyzes the real-world and simulated timing of both loops.
Table 3. Timing Analysis of Figure 3
| ||Real-World Time||Simulated Time|
|While Loop||183 ticks||12 ticks|
|Single-Cycle Timed Loop||1 tick||1 tick|
Notice that the real-world time and simulated time for the While Loop in Figure 3 are not equivalent. In real-world time, the single-cycle timed loop (SCTL) iterates 183 times faster than the While Loop, whereas in simulation mode, the SCTL iterates only 12 times faster than the While Loop.
This is because the While Loop does not contain any nodes to enforce timing in simulation mode. While it is acceptable not to specify timing for a While Loop, adding a Loop Timer Express VI allows more accurate control of the execution time and makes simulation timing accurate to real-world timing. Figure 4 shows an example VI, modified based on the previous example, that contains a Loop Timer Express VI.
Figure 4. Using the Loop Timer Express VI to Enforce Proper Simulated Timing
After adding a Loop Timer Express VI with a value greater than or equal to the real-world time to the While Loop, the simulation timing and real-world timing of the While Loop are equivalent. FPGA code with parallel data paths or loops will not simulate accurately relative to each other unless simulated time is properly enforced.