Implementation of the First SEFDM 5G Transceiver Prototype Using LabVIEW Communications System Design Suite and USRP RIO

"We estimate that using LabVIEW with the USRP RIO saved us approximately six months in comparison to using the FPGA toolkits for MATLAB."

- Waseem Ozan, University College London

The Challenge:

Billions of devices will soon be connected to the Internet in line with the vision of the Internet of Things (IoT). This means 5G must make highly efficient use of the wireless spectrum. Spectrally efficient frequency division multiplexing (SEFDM) has the potential to make better use of the spectrum through bandwidth compression, however at the cost of a higher level of interference. Our challenge was to create a real-time testbed, on an industrial platform, to allow the world to investigate SEFDM.

The Solution:

We demonstrated the world’s first real-time SEFDM system using USRP RIO and the LabVIEW Communications System Design Suite. The key innovation is in the deployment of a novel real-time channel estimation and equalisation algorithm, combined with a real-time iterative detector. Our system compresses transmitted signal bandwidths up to 60% (for BPSK) and 30% (for QPSK), offering significant bandwidth savings, thereby satisfying one of the key challenges of 5G deployment.


Waseem Ozan - University College London
Ryan Grammenos - University College London
Hedaia Ghannam - University College London
Paul Anthony Haigh - University College London
Izzat Darwazeh - Find this author in the NI Developer Community




Our proposed SEFDM system saves bandwidth by compressing traditional orthogonal frequency division multiplexed (OFDM) subcarrier spacing beyond the orthogonality limit, thus increasing spectral efficiency. This enhancement in spectral efficiency translates directly into a gain in capacity, which is of paramount importance to network operators who could use this technique to add an additional 30 to 60 percent number of subscribers (depending on the modulation format) without higher spectrum licensing costs. Hence, SEFDM becomes a timely and key technique for future 5G communication systems and beyond.


SEFDM, originally developed at University College London (UCL) in 2003, has been the focus of increased interest. Over the last decade, SEFDM systems have been demonstrated through many research publications and laboratory experiments. However, only offline systems have been demonstrated, which simplifies the problem and avoids system-level development at the FPGA level.  In this work, we created a real-time system implementation for the first time. This is an important milestone, since the literature typically argues that real-time implementation of SEFDM systems is difficult due to the high level of complexity at the receiver.


Testbed Software and Hardware

To prove the SEFDM concept in real hardware transceivers and test the signals in realistic channels, we carried out two steps. First, we developed and implemented the software design using the LabVIEW Communications System Design Suite, which enabled the rapid development, test and deployment of a system prototype. Subsequently, we synthesised the code for an FPGA using a USRP-2953R software defined radio, to generate the radio frequency signals and modulate them into the SEFDM format. The LabVIEW Suite does this automatically, which was a great advantage because it meant that we only needed to work with the FPGA hardware at a high level.


The second step was deploying the hardware in a real-world mobile environment over a realistic channel where we employed the Spirent-VR5 channel emulator. We used the LTE EPA5 wireless channel model in this work (others are applicable and have been tested but are not shown here). The USRP RIO devices operate over the 1.2 GHz-6 GHz frequency range, meaning we can use standards such as IEEE 802.11 and LTE, without loss of generality. The device operates with a 120 MHz sampling frequency that can support video transmission and reception. We also demonstrated over-the-air transmission using two 2.4 GHz antennas as shown in the video.


Testbed Description

The software design consists of three parts: SEFDM generation and transmission, channel estimation and equalisation, and signal detection.


At the transmitter, we generated a stream of pseudorandom bits, which are encoded by a recursive convolutional coder of code rate R_c=1/2, where the forward polynomial (G1) is G1=1+D+D^2 and the feedback polynomial (G2) is G2=1+D^2. The coded bits are interleaved by a block interleaver before being mapped onto the appropriate constellation. We can test binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM).


Next, we converted the serial symbols into parallel streams and then used an inverse fast Fourier transform (IFFT) for modulation into SEFDM symbols, where the distance between subcarriers is compressed by a factor α≤1, relative to OFDM signals, where α=1.


In the final stage of the transmitter, the complex signal is fed into the FPGA inside the USRP RIO, which then feeds the signal to the necessary D/A converter, before up-conversion of the signal by a local oscillator to the 2 GHz band.


World First

In our application, we used a novel method to estimate the channel effect for the SEFDM system. One of the key challenges previously established is that when using bandwidth-compressed pilots (that is, using an SEFDM symbol as a pilot) they are not only impaired by the channel, but also by the inter-carrier interference between the subcarriers, which seriously degrades the channel estimate. In this work, the pilot is sent as an OFDM symbol, but at a lower rate compared to SEFDM symbols. This is because in SEFDM the separation between subcarriers is reduced compared to conventional OFDM. Therefore, we design our OFDM pilot so that the frequencies of the subcarriers equal those of SEFDM but without the inter-carrier interference, which makes these pilots orthogonal. This does not impact the system performance since the pilot carries no user information. This results in clean pilots, allowing the use of a simple one-tap equaliser in the frequency domain to mitigate the effect of the channel.


Recovering the Signal

To recover the transmitted signal, we developed an iterative detector based on a turbo equalisation technique with an interference canceller (shown in red in Figure 1), which depicts the process of recovering the transmitted signal. The equalised data is de-mapped and de-interleaved at the beginning of each iteration before Viterbi decoding. The correlation matrix has information about the interference generated between the self-interfering SEFDM subcarriers. We can use the estimated correlation matrix and the decoded data to estimate the interference generated between the SEFDM subcarriers.



After subtracting the estimated interference from the received signal, the resulting signal passes back into the decoding process to enhance the interference cancellation; repetition of this process leads to a better estimate of the transmitted data.


Figure 2 shows the detected signal after each iteration, where we used a compression factor of 30 percent (α=0.7) QPSK-SEFDM. It is clear that the symbols are recovered, error free, using our new channel estimation and equalisation method in combination with an iterative detector.


Worldwide Benefits

We plan to make the code open source and available online so that the research, industrial and equipment manufacturer communities anywhere in the world can experiment with and develop the system and consider it for future standards. The designed and implemented system is fully interactive for different parameters, such as number of subcarriers, type of pilot symbols, and the compression factor (α) so that users can fully appreciate how the parameters will affect their designs. This will impact 5G research and other wireless systems, powering high-quality and high-bit-rate services in a reduced wireless spectrum, which can lower the cost of future systems.


Working With NI

We chose the USRP RIO and LabVIEW Communications System Design Suite together as they provide a powerful and flexible technology platform to build and prototype our system. We ran the original simulation using The MathWorks, Inc. MATLAB® software. However, when it came to implementing the code on the FPGA, we found it to be significantly faster to use LabVIEW. This is thanks to the LabVIEW Suite handling the minute details of FPGA programming, which would otherwise require a steep learning curve if dealt with by the user. We estimate that using LabVIEW with the USRP RIO saved us approximately six months in comparison to using the FPGA toolkits for MATLAB.


Since this was our first time using NI hardware and software, we sat a three-day LabVIEW Communications training course to get us up and running quickly. We also had one day of support from an NI systems engineer to could answer our questions and to help us progress even faster with our work. Our initial link with NI was with the sales teams in the UK. We have recently extended our links to their research teams (in Dresden, Germany) as well as their educational training teams (in Austin, Texas) and have regular virtual meetings to enhance the system design. This has been very valuable in helping us complete this project in a reasonable time period.



This work introduces a world-first, experimental, real-time implementation of baseband generation, signal assembly, signal decoding, and a novel frequency domain channel estimation and equalisation method.


Using USRP-2953R with LabVIEW Communications System Design Suite was the right choice to build and rapidly prototype a communication system, in order to realise a real-time SEFDM demonstrator along with the associated software.



This work was part funded by the Engineering and Physical Sciences Research Council (EPSRC) “Discovery to Use Impact Acceleration” award for the development of a pre-commercialisation 5G transceiver prototype. The work was also supported by National Instruments and by a generous donation of the LTE FPGA core through the Xilinx University Program (XUP).


Author Information:

Waseem Ozan
University College London

Figure 1. Our SEFDM System Created With LabVIEW Communications System Design Suite and USRP RIO
Figure 1. Schematic Block Diagram of SEFDM System (blue shows the transmitter; brown shows the RF signal transmission, reception, and channel; green shows channel estimation and equalisation; and red shows the iterative detection with interference cancellation)
Figure 2. SEFDM Iterative Detector Showing Perfect Signal Recovery After Three Iterations While Saving 30 Percent Bandwidth