When compiling code for FPGA devices where designs can take long amounts of time to complete, errors resulting in failed compilations can be frustrating. Sometimes simply recompiling can solve the problem, while other situations may require significant design optimizations to succeed. When improvements and code changes are needed an understanding of how the errors relate back to the initial design can greatly streamline the necessary troubleshooting. This document covers many common errors that you may encounter when compiling FPGA code. For each error, a brief description and troubleshooting suggestions are provided. While not all possible compilation errors are covered, many common errors will report similar issues or follow the same troubleshooting process. For more specific details on recommendations in this document, refer to the LabVIEW Help or the Additional Resources section at the end of this document.
Once a compilation has been started, you can check the status and results of the compilation in the Compilation Status Window. If the compilation has failed, the Summary report will display the errors and other details. You can also view the Xilinx log for a detailed report, including the errors listed. You can save the log for future reference by clicking Save when viewing the Xilinx log report.
Note: It is normal to get several warnings in the Xilinx logs - even in successful compilations. You can ignore the warnings when identifying areas to troubleshoot. Focus on specific errors first, and only worry about warnings if they are known to be a problem for other reasons.
The following are common Xilinx error codes that can be thrown due to resource limitations when you compile your LabVIEW FPGA design:
|Xilinx Error||Possible Causes||Specific Suggestions|
|Pack:2310||Overuse of FPGA resources such as Slices, LUTs, BRAM, DSPs, and Multipliers. This error is the Xilinx ISE compiler’s typical resource limitation error.||Follow the general troubleshooting steps below for resource limitation errors.|
|Place 30-487||Overuse of FPGA resources such as LUTs and Flip Flops. This error is the Xilinx Vivado compiler’s typical resource limitation error.||Follow the general troubleshooting steps below for resource limitation errors.|
|Place:543||Overuse of resources due to design complexity resulting in difficulty placing the design.||This error is more complex, but the general troubleshooting steps below are a good place to start. If you cannot make progress using those steps, reach out to NI Support for further guidance.|
|Place:665||Overuse of BlockRAM and Multiplier resources, specifically on Xilinx Spartan-3 based FPGA devices. This is because these items share routing resources in the FPGA chip fabric.||Since this error is more targeted, focus on the portions of your FPGA code which use BlockRAM or multipliers. Try to reduce the usage of these specific resources.|
|Place 30-380||Too many Slices needed to place or fit the design. This error appears to be a result of extra resources needed to place and route the design.||Follow the general troubleshooting steps below for resource limitation errors. If you cannot make progress, reach out to NI Support for further assistance.|
|Place 30-4||Overuse of FPGA resources such as LUTs and Flip Flops.||Follow the general troubleshooting steps below for resource limitation errors.|
|Place 30-99||Overuse of FPGA resources such as LUTs and Flip Flops.||Follow the general troubleshooting steps below for resource limitation errors.|
These errors generally indicate that the design requires more physical resources to implement than are available on the FPGA. You may see that estimated usages are within acceptable levels despite the errors, so it can be difficult to determine areas to focus on. The following are general tips that can help you compile your projects successfully if you encounter a resource limitation:
LabVIEW FPGA will typically catch timing errors and populate them to users in the Timing Violation Analysis Window as opposed to specific compilation errors. This window will appear any time a compilation fails due to timing violations in LabVIEW FPGA code, and will list out each code path that failed timing. Double-clicking on items in each path will take you directly to the block diagram component responsible.
The following are suggestions for improving timing in your FPGA code:
Sometimes the compilation window displays the following message instead of a specific error: "LabVIEW FPGA: Some of the compilation steps were not executed." This message is indicative of many different problems and requires narrowing down the behavior to determine the exact problem. Some common causes of this behavior are crashes of the Xilinx compiler tool due to a lack of memory, or a loss of the connection with the compiler by LabVIEW FPGA.
To narrow down the issue, try the following troubleshooting steps:
The following table covers some of the other common errors you may encounter:
|Xilinx Error||Possible Causes||Specific Suggestions|
|Common 17-39||Indicates that the compilation failed due to a previous error and is typically not the cause of a failure on its own.||Look in the Xilinx log to determine the original error for further troubleshooting.|
|Synth 8-2139||This error can occur when code in an IP Integration Node results in terminals which use extended identifiers, and this is a known issue. For example, using an identifier such as “\myInput\” can result in an identifier of “prefix_\myInput\” which is an illegal identifier.||Ensure that the IP you are importing does not include extended identifiers as inputs or outputs.|
Here are some additional tips if you encounter the errors above, or other errors not listed in this document: