NI DSA and SC Express devices and modules typically only have analog input or analog output systems. There are specifications unique to DSA or SC Express, but also some specifications which apply to both. This section is organized in three sections to cover the common specifications, DSA analog input specific, and SC Express analog input specific.
Common Analog Input Specifications
Analog-to-Digital Converter (ADC) Type
Successive Approximation Register (SAR)
An ADC which converts an analog signal into a discrete digital representation by using a binary search to match a created voltage to the provided signal voltage.
An ADC architecture consisting of a 1-bit ADC and filtering circuitry which over-samples the input signal and performs noise-shaping to achieve a high-resolution digital output.
This terminology applies only to modules with delta-sigma ADCs. Delta-sigma ADCs use sample rates that are large multiples, such as 128 times the Nyquist rate for a given signal. For example, to sample a 25 kHz signal, a sample rate greater than the Nyquist rate (that is above 50 kHz) would be sufficient. However, a delta-sigma ADC using an oversample rate of 128 times, samples the signal at 6 MHz. This approach has several benefits, such as better anti-aliasing and higher resolution.
The oversampled data is processed by a digital filter within the ADC before the data is made available as an output. Since it takes a non-zero amount of time for the oversampled data to be processed by the digital filter, the output data rate is always lower than the oversample rate. The output data rate equals to the oversample rate divided by the ADC decimation ratio.
Resolution is the smallest amount of input signal change that a device or sensor can detect. The number of bits used to represent an analog signal determines the resolution of the ADC.
The NI PXIe-4300 is a 16-bit device, which means that lowest amplitude change that can be detected on the ±5 V range is 0.152 mV. On the ± 0.1 V range, this value is 3.05 µV.
This specification will state what frequencies are available to be used as the timebase frequency.
Specified typically in ppm, this specifies how far from the listed frequency the actual timebase frequency can be. This specification is subject to the device's cal interval spec.
This will state what external routes are available to be used as external timebases.
Typically shown in a table, this will show based on the reference signal provided what are valid locking frequencies for reference clock synchronization.
This will display what are valid reference clock sources for the device. This will typically consist of the onboard clock and the chassis backplane clock.
Filter Group Delay (ADC Filter Delay)
This filter delay is the result of the signal passing through an analog filter on the device. The values of this will vary based on the range/gain being used on the device.
Digital Filter Delay
Uncompensated Group Delay
This filter delay is the result of the following: analog filter delay, buffered mode digital filter, or hardware-timed single point mode filter. This delay is not compensated for when synchronizing and will need to be accounted for to not see a phase shift in the data.
Compensated Group Delay
This filter delay is the result of the anti-aliasing filter working in a bufered mode. When synchronized with other hardware this delay will be automatically compensated for.
Base Filter Group Delay
This delay is of a result of the signal passing through the digital anti-aliasing filter on the device. It is a partial component of the Compensated Group Delay spec, and is determined by the input frequency provided to the module.
Variable Filter Group Delay
This delay is of a result of the signal passing through the digital anti-aliasing filter on the device. It is a partial component of the Compensated Group Delay spec and is determined by the sample rate currently being used on the module.
Bandwidth/ Alias Rejection
Passband/ Alias-Free Bandwidth
The passband/Alias-Free Bandwidth is the defined as the frequency range starting at DC to the point where the anti-aliasing filter reaches its' -0.1 dB point. This range is where the signal being measured should exist to get a proper measurement
The PXIe-4464 lists its Alias-free bandwidth (BW) (passband) as "DC to 0.454 * fs" meaning from DC to 0.45 4 times your sample frequency will be the passband for your current measurement
The stopband/alias rejection is defined by 2 parts, an attenuation or rejection spec as well as a frequency spec. The attenuation/rejection defines the minimum amount of attenuation that will be applied to the signal, while the frequency determines where the starting point for that attenuation will occur.
The specification for the PXIe-4330 is shown below.
For the PXIe-4330 this means that signals found at a frequency of 0.55 times the sample frequency will see an attenuation of 100 dB from the original signal.
Minimum Frequency for Alias Hole
The delta-sigma ADCs on devices include an oversampled architecture and sharp digital filters with cut-off frequencies that track the sampling rate. Due to how the digital filter is designed inside of the ADC, there becomes a small hole, where in theory aliases could be seen, at larger frequencies.
Rejection at Alias Hole
To combat the alias holes left by the ADC an analog fixed frequency filter is applied to high frequency components along the analog path. This specifies what rejection those high frequency components will see.
Common Mode Rejection Ratio (CMRR)
When the same signal is seen on the positive and negative inputs of an amplifier, the CMRR specifies how much of this signal is rejected from the final output (typically measured in dB). An ideal amplifier will remove 100% of the common mode signal, but this is not achievable in implementation.
The NI PXIe-4300 has a CMRR of 100 dB for the 5 V range. This means that it will attenuate common mode voltages by 100,000x. If the signal being measured is a 5 Vpk sine wave, and the offset or common voltage between the positive and negative inputs is 5 VDC, the final output will reject or attenuate the 5 VDC input to 5 µV. CMRR is not included in accuracy derivations and should be accounted for separately if the signal measured contains common mode voltages.
The measure of how much a signal on one channel can couple onto, or affect, an adjacent channel. Crosstalk exists any time an amplitude-varying signal is present on a wire or PCB trace that is physically close to another wire or PCB trace.
The NI PXIe-4464 has a crosstalk specification of -95 dB for adjacent channels and -125 dB for non-adjacent channels when using its’ -10 dB Gain range. This means that channel ai2 will have a crosstalk specification of -95 dB between channels ai1 and ai3, and a crosstalk specification of -125 dB to all other ai channels.
Some modules such as the NI 4461 and NI 4464 support both DC and AC coupled modes. When DC coupling mode is selected, any DC offset in the source signal is passed on to the ADC. When AC coupling mode is selected, a high pass filter is enabled at the input of the signal path, filtering out most DC content of the signal.
See Also: Basic Information about AC and DC Coupling.
Specifies what type of out is provided when requesting excitation from a module. For SC Express this will typically be listed as “Constant Differential Voltage (Balanced)”.
Provides the noise found on the excitation line as well as what bandwidth said noise was measured with. Typically represent in uVrms.
Values/ Voltage Programmability
Specifies what voltage values are available to be provided by the internal excitation form the module.
Maximum Fault Current
Is the maximum current that the module can possibly provide in the case of a fault in the external circuitry.
Minimum Current/ Maximum Current/ Current Drive
Is the smallest max current we guarantee that the module will be able to provide through excitation.
LVDT Module Specific
Specifies what voltage values are available to be provided by the internal excitation form the module.
Specifies what frequency values can be selected by the device for the provided excitation.
Is the smallest max current we guarantee that the module will be able to provide through excitation.
Is the accuracy in the gain of the provided excitation voltage from the module.
A range for the output of the excitation the user is able to select any values inside said range that are compatible with the corresponding adjustment resolution step size.
Is the capability to maintain a constant voltage (or current) level on the output channel of a power supply despite changes in the supply's load.
Current Limit Detection
Is a software readable property of the excitation that will change based on comparing the current excitation current to the specified limit current.
IEPE Open Detection
Is a software readable property for the module that will tell the user if the circuit is currently open.
IEPE Short Detection
Is a software readable property for the module that will tell the user if the circuit currently has a short.
Specified as either a value or value min, the compliance voltage is minimum max value that Vcommon-mode + Vbias + Vfull-scale will add up to. Where
Vcommon-mode is the common mode voltage seen by the input channel Vbias is the DC bias voltage of the sensor Vfull-scale is the AC full scale voltage of the sensor.
A balanced source uses three conductors to carry the signal. Two of the conductors carry negative and positive signals (AC signal), and the third is used for grounding. The high gain and isolated ground make for a cleaner, noise-free signal when using a balanced source.
An unbalanced source, there are only two conductors. One carries positive, the carries negative and is also used for ground. Better for short cables found in low noise environments.
FIFO Buffer Size
NI DAQ devices can store data in an onboard FIFO when performing analog input or analog output tasks.
- For input tasks, this FIFO is used to buffer data prior to the NI-DAQmx driver software transferring the data to a pre-allocated location in RAM known as the PC buffer.
- For output tasks, the data that a user requests to generate can be buffered in a combination of the FIFO and the PC buffer.
Devices that have input and output channels will have a dedicated FIFO for each subsystem. However, the FIFO is shared across all channels within that FIFO. For analog input, NI-DAQmx implements data transfer mechanisms to ensure that the data stored in the FIFO is transferred to the PC buffer fast enough so that the onboard FIFO is not overrun. For analog output, NI-DAQmx implements data transfer mechanisms to ensure that data in the PC buffer is transferred to the onboard FIFO fast enough such that the FIFO is not underrun. For analog output, there are user-selectable properties to specify whether to use the PC buffer at all, and to regenerate a single waveform from just the onboard FIFO.
The signals within a passband have frequency-dependent gain or attenuation. The small amount of variation in gain with respect to a reference frequency is called the passband flatness.
Frequency Response (Magnitude and Phase)
As a frequency sweep is performed across the analog input of a module the magnitude and phase of the measured signal will change based on filter characteristics of the module. This data is typically represented in either a chart or a table of frequency values.
Gain error inherent to the instrumentation amplifier and is known to exist after a self-calibration.
Input impedance is a measure of how the input circuitry impedes current from flowing through to analog input ground. For an ideal ADC, this value should be infinite—meaning no current will flow from the input to ground—but in practice this is not possible. The implication of some finite input impedance is that the ADC will have some degree of loading down a circuit, particularly those of high output impedance. It is typical for sensors to have low output impedance.
The NI PXIe-4309 has an input impedance of Zin > 10 G Ω. Taking the worst-case scenario of lowest input impedance, you can view a single-ended measurement as the following simplified circuit, assuming a sensor with output impedance Zout = 150 Ω.
The series combination of the sensor output and DAQ device input means that voltage will be divided between the two impedance values, with the larger impedance bearing most of the voltage. This means that if the sensitivity of this sensor is 20 °C / V and is measuring 100 °C (outputting 5 V), then the voltage measured by the DAQ device will be the output voltage multiplied by the ratio of the input impedance to the sum of the DAQ input and sensor output impedance:
This 75 nV measurement difference corresponds to a near-negligible 1.5u °C measurement error due to impedance.
To illustrate an example when input impedance becomes an important specification, take the hypothetical case where a sensor has an extremely high output impedance, such as 5 GΩ. Connecting the DAQ device to a sensor with this extremely high output impedance causes a 5 V nominal output from the sensor to be read as 3.333 V, or a hypothetical measurement error of 33.34 °C.
Additional system noise generated by the analog front end, measured by grounding the input channel.
Isolation is the means of physically and electrically separating two parts of a device. It protects computer circuitry and human operators, breaks ground loops, and improves common-mode voltage and noise rejection.
Each channel is isolated from every other channel and other non-isolated components. The figure below represents channel-to-channel isolation. Va,b, Vc,d, Ve,f, and Vg,h are all on separate buses and are isolated from one another.
Channels of the device and the device's Earth ground are electrically isolated from one another. Channel-to-Earth isolation is represented in the Figure below. Voltages of the isolated front end (Va-c ) are on the same bus; these voltages are not isolated from one another. Ve,d are on a separate bus and are isolated from the front end.
Interchannel Gain Mismatch
Channel-to-channel gain mismatch defines the difference in gain on any given channel relative to a reference channel. It is specified as a function of the input frequency.
Interchannel Phase Mismatch
Channel-to-channel phase mismatch defines the difference in phase on any given channel relative to a reference channel. It is specified based on the measurement range and the input signal frequency of the measurement
NI 4302 in the 10V range specifies channel-to-channel gain mismatch of fin * 0.035°/kHz maximum. For example, if the input signal frequency is 2 kHz, the maximum difference in phase on one channel relative to any other channel on the module. is 0.07°.
Offset (Residual DC)
Offset error inherent to the instrumentation amplifier and is known to exist after a self-calibration.
The analog input circuitry has protection diodes in place that will gate a large voltage from damaging the most critical components of the device, such as the PGIA or ADC.
- When the device is powered on, these diodes are biased at some positive and negative voltage, meaning that a voltage larger than the sum of the bias and reverse voltage must be present before these diodes are overloaded and can be damaged.
- When the device is off, the bias voltage is removed, so the voltage needed to reverse the diodes is lower, making the device more susceptible to being damaged.
When in an overvoltage state, the maximum amount of current that a device can sink is specified by the input current during overvoltage condition.
The NI PXIe-4480 has protection up to ±30 V for two AI positive pins. If more than two AI pins experience an overvoltage larger than ±30 V, the device can be damaged. While the device is off, there is a lower level of protection at ±15 V.
Ideally in a linear phase system, the phase and the frequency of the signal have a linear relationship. This means that input signals of all frequencies have the same time delay through the system. Phase non-linearity is an expression of the extent to which the phase-frequency function deviates from the ideal.
For analog input, this is the maximum positive and negative value that can be measured with guaranteed accuracy. For analog output, this is the maximum positive or negative value that can be generated. Some devices have multiple input or output ranges that can be used to provide a higher resolution at lower level signals.
The NI PXIe-4300 has four input voltage ranges: ±1 V, ±2 V, ±5 V, and ±10 V.
Typically provided as channel-to-earth ground, this is the measure of how far the differential signal can stray from earth ground while still providing correct measurements.
Maximum Working Voltage
The maximum working voltage is determined by taking the signal voltage and them adding the common voltage to it. In most instances where this is specified the maximum working voltage will vary based upon what signal range is currently in use.
The signal range specifies the maximum and minimum values that has been configured to be handled by the ADC. This is a user selectable property when setting up DAQmx Tasks. Providing too small of a range will result in the signal clipping at the maximum and minimum values, while providing too large of a range will result in a worse resolution in the measurement.
A useful specification when measuring thermocouples, sensitivity defines based on timing mode what the smallest change in temperature can be recorded by the device. This specification is currently only used on the PXIe-4353.
This specification covers how a variety of specifications can change based on either time or temperature. As a result, this specification will typically alter other specifications based on a temperature difference, or a time since last calibration.
Sample rate range specifies what values are available for how often an ADC converts data from analog to digital values. Some devices have only one ADC, so the sample rate is shared across channels while other devices have a dedicated ADC per channel. Sample rate is measured in Samples per second (S/s) or Samples per second per channel (S/s/ch) when acquiring from multiple channels.
- Single Channel Maximum—For a shared sample rate across channels, a single channel can acquire data at a higher rate than allowed when sharing
- Multichannel Maximum—For a device that shares the sample rate across channels, this is the maximum rate at which all channels combined can acquire data
- Minimum—The minimum rate at which data can be acquired
Sample and update rates for analog input and output tasks are restricted to discrete values when using an onboard timing engine. The difference in clock periods between two adjacent rates is known as timing resolution. NI-DAQmx will coerce a selected frequency up to the next available frequency if it cannot generate the exact one specified by the user.
The NI PXIe-4300 has a specified timing resolution of 10 ns. This means that it can generate or acquire data at integer multiples of 10 ns. For example, 32,000.00 Hz and 32,010.2432... Hz are two adjacent frequencies, as their clock periods are 31.250 µs & 31.240 µs, respectively. To find the next available frequency, add or subtract the timing resolution to a known clock period.
Spectral Noise Density
While it can be shown in 2 different methods, this specification is the representation of noise across the spectral range of the device. It can be shown either based on the current frequency being measured or based on the current range of the module. This specification is typically given in Volts per square root Hertz.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the usable dynamic range before spurious noise interferes with or distorts the fundamental signal. Analog input and analog output circuitry both have non-linearities that result in harmonic distortion. SFDR is easily observable in the frequency domain as:
The PXIe-4339 has an SFDR of around 100 dB. Taking the graph above as an example, if the fundamental signal was applied at 0 dB, the next highest spur would occur at 100 dB lower - providing a usable dynamic range without spurious interference.
Total Harmonic Distortion
Due to inherent nonlinearities of ADC and DAC components, harmonic frequencies will appear in the measured or generated signals. The ratio of the sum of these harmonics' powers to the power of the fundamental is known as total harmonic distortion.
The PXIe-4480 has a specified THD of -100 dB when fs = 51.2 kS/s. This means that for a given test signal, in this case a 10 kHz sine wave at full scale, the amplitude of the signal attributed to harmonic distortion is less than 0.001%. Conversely, more than 99.999% of the amplitude that is measured can be attributed to the fundamental tone or signal of interest.