This memory interface provides the easiest-to-use FIFO interface to external DRAM. The FIFO is exposed as separate read and write interfaces. Both the write-side and read-side data ports are 64-bit data words.

Signals for Writing to the FIFO

The following table lists the write-side I/O provided by the FIFO - 64 Bit memory interface.

Memory Interface I/O Data Type To Memory/From Memory Description
Full Bool From memory

TRUE = Indicates that the FIFO is full and that no data can be written to it.

FALSE = Indicates that the FIFO is not full and that data can written to it.
Write_Data_Upper U32 To memory Sets the upper 32 bits of the data to write into the FIFO.
Write_Data_Lower U32 To memory Sets the lower 32 bits of the data to write into the FIFO.
Write Bool To memory

TRUE = Transfers data from the Write_Data_Upper and Write_Data_Lower signals into the FIFO.

FALSE = Transfers no data to the FIFO.

Note Do not set the Write signal to TRUE when the Full signal is TRUE.

Signals for Reading from the FIFO

The following table lists the read-side I/O provided by the FIFO - 64 Bit memory interface.

Memory Interface I/O Data Type To Memory/From Memory Description
Data_Available Bool From memory

TRUE = Indicates that the values in the Read_Data_Upper and Read_Data_Lower signals are valid and may be read.

FALSE = Indicates that the values in the Read_Data_Upper and Read_Data_Lower signals are invalid and may not be read yet.
Read_Data_Upper U32 From memory Displays the upper 32 bits of the data to read from the FIFO. This signal is valid only when the Data_Available signal is TRUE.
Read_Data_Lower U32 From memory Displays the lower 32 bits of the data to read from the FIFO. This signal is valid only when the Data_Available signal is TRUE.
Read Bool To memory

TRUE = Reads data from the Read_Data_Upper and Read_Data_Lower signals out of the FIFO.

FALSE = Does not read any data from the FIFO.

Note Do not set the Read signal to TRUE when the Data_Available signal is FALSE.

The write-side interface Full signal is TRUE when data cannot be added into the FIFO. If the Full signal is low, you can write data into the FIFO by driving the Write_Data_Upper and Write_Data_Lower signals with your data and setting the Write signal to TRUE. Do not set the Write signal to TRUE when Full is TRUE because this condition leads to undefined behavior.

When read-side data on the Read_Data_Upper and Read_Data_Lower lines is available to be read, the Data_Available signal is TRUE. After this data is read, set the Read signal to TRUE. Do not set the Read signal to TRUE when Data_Available is FALSE because this condition leads to undefined behavior.

The FIFO - 64 Bit memory interface requires you to define the clock domains of the single-cycle Timed Loop from which the read-side and write-side interfaces are accessed. Configure these interfaces using the Clock Selections property page for the corresponding DRAM bank item in the LabVIEW project. Configure the Input_Clock signal to be driven with the LabVIEW FPGA clock resource which you are using to clock the single-cycle Timed Loop that is accessing the write-side interface. Likewise, configure the Output_Clock signal to be driven with the LabVIEW FPGA clock resource that you are using to clock the single-cycle Timed Loop that is accessing the read-side interface.

Note All memory interface signals must be used in a single-cycle Timed Loop. The clocks of this single-cycle Timed Loop must be specified as input clocks in the FPGA Base Clock Properties dialog box.
Note You must disable all synchronization registers for all DRAM FPGA I/O signals (by setting the value to 0). The DRAM interface signals are synchronous to the DRAM interface clock. Synchronization registers causes a delay in sending and receiving data/commands to/from the DRAM interface. This delay can prevent proper operation. Always disable synchronization registers for synchronous interfaces where proper operation depends on no latency. All NI PXI version 1.1 and later CLIP items and all NI PXI Express CLIP items automatically disable all synchronization registers. For more information about disabling synchronization registers, refer to the Advanced Code Generation FPGA I/O Properties Page.
Note Depending on clock rates and your application, it may take several clock cycles for data input to the FIFO to be read from the FIFO.

The FIFO - 64 Bit memory interface is designed to simultaneously read and write data at speeds up to 40 MHz. It is possible to run the interface up to 200 MHz. However, at speeds greater than 40 MHz, the Full and Data_Available signals may temporarily become TRUE and FALSE, respectively.

LabVIEW contains example VIs that read and write to the FIFO - 64 Bit memory interface. To access the NI Example Finder, open LabVIEW and select Help » ind Examples, then select Hardware Input and Output » FlexRIO. You can also access device-specific examples by selecting Add device from the Hardware pull-down menu in the NI Example Finder.