Use the FPGA I/O Method Node to invoke a method on an I/O item or hardware under an FPGA target. The I/O Method Node is located on the FPGA I/O Functions palette. You can use the following methods with this device.

Note The following methods apply only to the fixed I/O that automatically associates with the installed NI PXI-795x target.
Method Description
Set Output Data Writes data to the digital line or port without enabling the line or port. You can use the Set Output Data method to optimize performance when performing successive writes to a DIO resource. The data type of the Data input depends on the I/O item. For example, if the I/O item is a digital line, Data requires a Boolean data type.
Set Output Enable Determines whether the digital input and output resource reads external input or writes output. Wiring TRUE to Set Output Enable for a digital line allows the resource to write data. Wiring FALSE to Set Output Enable allows the resource to read external data. The data type of the Enable input depends on the I/O item. For example, if the I/O item is a digital line, Enable requires a Boolean data type, and if the I/O item is an 8-bit digital port, Enable requires a U8 data type. The binary values of the U8 input correspond to the individual lines of the digital port. Zeros correspond to FALSE inputs and ones correspond to TRUE inputs.
Wait on Any Edge

Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Any Edge method waits for the next falling or rising edge.

0 = Causes the method to timeout immediately.

Negative value = Causes the method to wait indefinitely.

Positive value = Causes the method to wait for that number of clock cycles before timing out.
Wait on Falling Edge

Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Falling Edge method waits for the next falling edge.

0 = Causes the method to timeout immediately.

Negative value = Causes the method to wait indefinitely.

Positive value = Causes the method to wait for that number of clock cycles before timing out.

Wait on High Level

Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on High Level method waits for the next logic high level.

0 = Causes the method to timeout immediately.

Negative value = Causes the method to wait indefinitely.

Positive value = Causes the method to wait for that number of clock cycles before timing out.
Wait on Low Level

Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Low Level method waits for the next logic low level.

0 = Causes the method to timeout immediately.

Negative value = Causes the method to wait indefinitely.

Positive value = Causes the method to wait for that number of clock cycles before timing out.

Wait on Rising Edge

Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Rising Edge method waits for the next rising edge.

0 = Causes the method to timeout immediately.

Negative value = Causes the method to wait indefinitely.