DRAM is optimized for high storage density and high bandwidth. DRAM accesses data sequentially and in large blocks. For example, you have to read the data in address 0x1 after you have read the data in address 0x0 and the processor reads large blocks of memory into cache, even if the program being executed requests a single byte.

To maximize performance, avoid switching between reading and writing, accessing noncontiguous addresses, or writing to memory in decrementing-address fashion. The most efficient access strategy is to perform only one type of access, either reading or writing, on a large number of sequential addresses. Although this is optimal, it is not practical for most applications. A more practical approach is to maximize the amount of sequential data being accessed and minimizing changes in access modes.

The Process VI in the Memory IDL has an arbiter configuration input that allows you to dynamically alter the number of sequential reads and writes (write grant time and read grant time). Use this functionality to dedicate 100% of DRAM bandwidth to reading only, writing only, or equally sharing bandwidth between reads and writes.