The onboard frequency generator on the digital waveform generators and analyzer uses a Phase-Locked Loop (PLL) circuit to lock the high-frequency internal timebase of the device to a known reference frequency. The most common clock to which the device is locked is the reference clock signal on the PXI or PXI Express backplane. This clock signal is shared among all modules in the system, so you can lock all the modules in your system to this stable clock. PXI_CLK10 is the 10 MHz reference signal that is available for PXI devices, and PXIe_CLK100 is the 100 MHz reference signal that is available for PXI Express devices. The NI-HSDIO API refers to PXIe_CLK100 and PXI_CLK10 as "PXI Clock."
Note PXI_CLK10 is available only on digital waveform generators and analyzers for the PXI bus. PXIe_CLK100 is available only on digital waveform generators and analyzers for the PXI Express bus. The onboard reference clock is a 10 MHZ clock signal that is available for use with digital waveform generators and analyzers for the PCI bus.

You can use the reference clock only when onboard clock is selected as the sample clock source for a dynamic generation or acquisition session.