Learn how to access and configure DRAM on FPGA targets using LabVIEW FPGA memory items.

Some FPGA targets contain onboard dynamic random access memory (DRAM) that you can access directly from the FPGA VI. LabVIEW supports DRAM access through FPGA memory items, which provide usability and VHDL optimization similar to block memory and LUT.

Accessing DRAM

Use the FPGA memory item interface in the project to access DRAM. DRAM memory items appear in the Project Explorer under the FPGA target.

You cannot use VI-defined memory items to configure DRAM.

Partitioning DRAM into Multiple Memory Items

You can partition physical DRAM banks into multiple memory items using the Memory Properties dialog. For example, if a target has two physical DRAM banks, you could partition one bank into three memories and the other into five. LabVIEW treats each memory independently.

Note Before you partition DRAM, verify that your FPGA target supports DRAM. See Check DRAM Availability on an FPGA Target for step-by-step instructions.
Figure 3. Example of Partitioning DRAM Banks into Multiple Memory Items

Diagram showing DRAM Bank 0 with three partitions and DRAM Bank 1 with five partitions.

After creating partitions, configure arbitration between partitions in the same DRAM bank using the DRAM Properties page of the FPGA Target Properties dialog.

Arbitrating Access to the DRAM Bank

If you partition the DRAM into multiple memory items, you can configure the amount of time LabVIEW grants to each partition. By default, LabVIEW grants equal time to all partitions. This DRAM arbiter is not the same arbiter that arbitrates between different requestors of the same shared resource.

Specify the time to grant each partition under FPGA Target Properties » DRAM Properties. LabVIEW grants time to each partition using round robin scheduling.

Understanding Latency and DRAM

Access to DRAM involves some non-deterministic latency. Perform the following steps to compensate for this latency:
  • Use the Request Data and Retrieve Data methods to read data from DRAM.
  • Queue multiple requests for data using Request Data and retrieve requested data using Retrieve Data.
  • DRAM returns requested data when you indicate readiness using handshaking signals.

To optimize performance, send requests for data or write data in bursts, such as on each clock cycle.