This document contains the FlexRIO known issues that were discovered before and since the release of FlexRIO 21.5. Known issues are performance issues or technical bugs that NI has acknowledged exist within this version of the product.
Not every issue known to NI appears on this list; it is intended to show the most severe and common issues that you may encounter and provide workarounds when possible. Other technical issues that you may encounter could occur through normal product use or system compatibility issues. You may find more information on these issues in NI’s Product Documentation, Knowledgebase, or Community.
|
Bug Number |
Legacy ID |
Description |
Details |
|---|---|---|---|
| 1042857 |
Estimated timing and final timing are grayed out in the Compilation window for the NI-7935After a successful FPGA compilation for a NI-7935, the Estimated timingand Final timing tabs in the FPGA Compilation Status window are grayed out and not selectable. Workaround: The FPGA compilation would fail if the desired timing constraints are not met. A successful compilation means your timing constraints were met. To manually verify successful compilation for clock timing constraints, you can check the FPGA compilation output XML file. The Route_Twx section will list PASS for clocks listed that successfully meet the timing constraints. The XML file is located here: C:\NIFPGA\compilation\\output_files.zip\lvParsedReports.xml |
Reported Version: FlexRIO 18.7 Resolved Version: N/A Added: Jan 8, 2021 |
|
| 230875 | 596974 |
When synchronizing multiple NI 5752 or NI 5752B FlexRIO Adapter Modules there may be one sample of uncertainty.Due to a known issue in the constraints of the CLIPs for the NI 5752 and 5752B FlexRIO Adapter Modules there may be one sample of uncertainty when attempting to send the AdcTgcStart signal to the ADCs on the adapter modules. This may cause the gain sweep to start at different samples between adapter modules. Workaround: There is currently no known workaround for this issue. |
Reported Version: FlexRIO 16.0 Resolved Version: N/A Added: N/A |
| 883400 | 545599 |
The Controller for FlexRIO (NI-793XR) does not support debugging FPGA VIs using a third-party simulator.The Controller for FlexRIO (NI-793XR) does not support the use of a third-party simulator to simulate and debug a LabVIEW FPGA VI. Workaround: There is currently no known workaround for this issue. |
Reported Version: FlexRIO 16.0 | NI-793xR 15.1 Resolved Version: N/A Added: N/A |
| 891271 | 554346 |
The Aurora CLIP shipped with the NI-793xR - MGT Aurora CLIP example may fail to initialize.A design using the Aurora CLIP from the NI-793xR - MGT Aurora CLIP example project may fail to initialize after downloading a bitfile or resetting the FPGA. Workaround: Use the status signals on the Aurora CLIP to determine if an error occurred and re-download the bitfile until the CLIP initializes without an error. |
Reported Version: FlexRIO 16.0 Resolved Version: N/A Added: N/A |
| 889041 | 555601 |
DRAM on NI PXIe-797xR FlexRIO FPGA Modules is inaccessible immediately after a download or reset of the FPGA.DRAM on NI PXIe-797xR FlexRIO FPGA Modules is inaccessible immediately after a download or reset of the FPGA. A wait of at least 2.5 seconds must be added before before accessing the DRAM after an FPGA download or reset. Workaround: After any reset or download of the FPGA, wait at least 2.5 seconds before accessing the DRAM. |
Reported Version: FlexRIO 16.0 | PXIe-797xR 15.0 Resolved Version: N/A Added: N/A |
| 531101 | 526736 |
In the Streaming instrument design library, Wait For Stream.vi can return an incorrect value for the Samples Transferred output when an FPGA target is executed in simulation mode.In the Streaming instrument design library, due to a race condition present only in simulation mode, Wait For Stream.vi can return the second to last Samples Transferred value rather than the expected terminal value of a finite transfer. Workaround: Do not use the Samples Transferred output from Wait For Stream.vi as the value for the Requested Elements input on a DMA FIFO when completing a finite transfer. |
Reported Version: FlexRIO 14.0 Resolved Version: N/A Added: N/A |
| 531617 | 624455 |
In the "NI 5783 - Getting Started" example, Data Clock setting is 125 MHz single frequency, which is inconsistent with x2 Data Clock (200 MHz).In the "NI 5783 - Getting Started" example, Data Clock setting is 125 MHz single frequency, which is inconsistent with x2 Data Clock (200 MHz). This inconsistency leads to a compilation error for certain IPs that require Data Clock and x2 Data Clock for overclocking. The error notes that the frequency is not within the requested range for the target. Workaround: Reload NI 5783 CLIP by disabling NI 5783 FAM and re-enabling NI 5783 FAM. |
Reported Version: FlexRIO 16.1 Resolved Version: N/A Added: N/A |
| 531516 | 722379 |
Premature overflow of dynamically arbitrated DRAM FIFOWhen the DRAM FIFO process VI is set to "dynamic (priority writes)" and the "from DRAM" queue is full there is a chance that the FIFO prematurely overflows. Workaround: Set the dynamic arbitration setting to "none" and use the "read grant time" and "write grant time" to arbitrate throughput. |
Reported Version: FlexRIO 18.6 Resolved Version: N/A Added: N/A |
| 1784832 |
Setting Serial Output Data Rate on a Channel on PXIe-1486 and PXIe-1487 Devices May Change the Data Rate on a Different ChannelThis issue impacts setting the serial output data rate on some channels for the PXIe-1486-02, PXIe-1486-03, PXIe1487-02 and PXIe-1487-03 devices. Workaround: Set a single data rate for all serial output channels for applications that do not require channel specific data rates. |
Reported Version: FlexRIO 21.0 Resolved Version: N/A Added: N/A |
Issues found in this section will not be listed in future known issues documents for this product.
There are currently no issues to list.
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