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Understanding LVDS for Digital Test Systems


This tutorial is part of the National Instruments Measurement Fundamentals series. Each tutorial in this series will teach you a specific topic of common measurement applications by explaining theoretical concepts and providing practical examples.

Continuous improvements in technology have resulted in devices that can produce and process data at rates that were unreachable in the past. This progress has led to the development of devices such as software-defined radios (SDR), high-performance data converters, and high-resolution flat panel monitors and televisions. As the ability to produce and process data increases, the transmission of this data from one point to another becomes the limiting factor for the overall system performance. In these circumstances, low-voltage differential signaling (LVDS) is gaining popularity as the solution to these bandwidth bottlenecks.

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What Is LVDS?

LVDS (low-voltage differential signaling) is a high-speed digital interface that has become the solution for many applications that demand low power consumption and high noise immunity for high data rates. Since its standardization under ANSI/TIA/EIA-644, LVDS has been implemented in a diverse set of applications and industries, discussed in the LVDS Applications section of this document. The LVDS standard provides guidelines that define the electrical characteristics for the driver output and receiver input of an LVDS interface, but stop short of defining a specific communication protocol, required process technology, media, or voltage supply. The general, non-application-specific nature of the standard has been conducive to the adoption of LVDS across a wide variety of commercial and military applications. Moreover, growing demands for bandwidth have resulted in the emergence of high-performance technologies such as PCI Express and HyperTransport, which are based on high-speed LVDS connections. The low power and high noise immunity aspects of LVDS, along with the abundance of commercial off-the-shelf (COTS) LVDS components has led many military and aerospace applications to select LVDS as a robust, long-term solution for high-speed data transmission.

Electrical Characteristics of LVDS

The LVDS standard defines the electrical characteristics of the transmitter and receiver of an LVDS interface. LVDS uses differential signals with low voltage swings to transmit data at high rates. Differential signals contrast to traditional single-ended signals in that two complementary lines are used to transmit a signal instead of one line. That is, two signals are generated of opposite polarity, and then the data transmission references the two signals to one another. This transmission scheme provides the kind of large common-mode rejection and noise immunity to a data transmission system that a single-ended system referenced only to ground cannot provide.

Figure 1 illustrates a typical LVDS transmitter. This transmitter consists of a current-mode driver, which provides around 3.5 mA of current through the transmission lines of the differential pair. At the receiver, a 100 Ω termination resistor is used to match the impedance of the transmission line that connects the receiver to the driver. Closely matching the impedance of this termination resistor with the impedance of the transmission lines reduces harmful signal reflections that decrease signal quality. The termination resistor also provides a path between the complementary signal paths of the system. The high input impedance of the receiver causes the 3.5 mA current coming from the driver to flow through the 100 Ω termination resistor, resulting in a voltage difference of 350 mV between the receiver inputs. As the path for the current within the driver changes from one path to another, the direction of the current flowing through the termination resistor at the receiver changes as well. The direction of the current through the resistor determines whether a positive or negative differential voltage is read. A positive differential voltage represents logic-high level, and a negative differential voltage represents logic-low level.

Figure 1. LVDS Driver and Receiver

As mentioned previously, the ANSI/TIA/EIA-644 standard provides a set of specifications to which all LVDS devices must adhere. Figure 2 shows a differential signal labeled with some of the key parameters defined by the standard.

Figure 2. Parameters of a Differential Signal

The first parameter is the differential output voltage (VOD). This voltage is the absolute value of the difference in voltage measured between the two output lines of the driver and is specified to be between 247 and 454 mV, with 350 mV being typical. VOH and VOL are voltage output high and voltage output low, respectively. These parameters are not specified for LVDS devices, but you can determine them by combining the output offset voltage range (VOS) with the differential output voltage (VOD). VOH and VOL are the output voltages of the driver with respect to ground and should always be within the input range of the receiver.

The standard defines the input voltage range of the receiver, VIN, to be 0 to 2.4 V. This input voltage range is significantly larger than the range of expected voltages from the driver. This difference provides the ability to absorb and reject common-mode noise, noise that is present on both lines of the differential pair, and allow for offsets between the driver and the receiver. Refer to Figure 3 for an illustration of this common-mode noise rejection.

Figure 3. Common-Mode Noise Rejection by the Receiver

The offset voltage is the common-mode voltage of the differential signal and is essentially the average voltage of the two lines of the differential pair with respect to ground. The minimum and maximum values for VOS according to the standard are 1.125 and 1.375 V. A typical value for VOS is 1.2 V. This value places the differential signal in the center of the voltage input range, VIN, for the receiver. With a voltage swing of 350 mV centered at 1.2 V, a margin of 1.025 V is available on each side of the signal. With this margin, the receiver effectively rejects common-mode noise and ground shifts within this margin.

Another important parameter is threshold voltage (VTH) of the receiver. The threshold voltage is the minimum difference in voltage between the lines of the differential signal that can be registered as a valid logic state. This voltage is specified as |100 mV|; therefore, the positive line of the differential pair must be at least 100 mV greater than the complementary line for the receiver to register logic high level, and the positive line must be at least 100 mV less than the complementary line for the receiver to register a logic low level. Compared to other differential technologies, LVDS and its derivative have some of the lowest voltage swings. This low voltage swing is one reason why LVDS can achieve very high data rates while consuming lower power than other available data transmission technologies. Smaller swings require less power and result in faster transition times between logic states, which is a key factor in the overall data bandwidth of a transmission path. ANSI/TIA/EIA-644 specifies that the maximum data throughput of a system is dependant on the transmission times of the signal. This relationship is expressed in a maximum output rise and fall time specification of 30% of the unit interval. For example, in order for a system to be classified as 1 Gb/s (unit interval of 1 ns), the signals must have rise and fall times smaller than 300 ps (30% of 1 ns). Refer to Figure 4 for a comparison of voltage swings for several common differential technologies.

Figure 4. Comparison of LVDS with Other Differential Technologies

Another feature defined by the LVDS standard is the LVDS fail-safe feature. In an LVDS interface, the fail-safe specification forces the receiver to provide logic-high level under certain input conditions. The receiver will output a logic high when one of the following conditions is true:

  • The driver is disconnected from the receiver or powered off while the receiver is still powered on.
  • The two lines of the differential pair become shorted.
  • The inputs of the receiver are left open.

This fail-safe mode prevents the receiver from providing invalid data because of unexpected voltages on inputs.

Benefits and Advantages of LVDS

The differential nature of LVDS has many inherent advantages. The most fundamental of these advantages is the ability to reject common-mode noise. When the two lines of a differential pair run adjacent and in close proximity to one another, environmental noise, such as EMI (electromagnetic interference), is induced upon each line in approximately equal amounts. Because the signal is read as the difference between two voltages, any noise common to both lines of the differential pair is subtracted out at the receiver. The ability to reject common-mode noise in this manner makes LVDS less sensitive to environmental noise and reduces the risk of noise related problems, such as crosstalk from neighboring lines. As a result, LVDS can use a much lower voltage swing compared with traditional single-ended schemes that rely on higher voltage swings to maintain an adequate threshold for noise tolerance.

The differential nature of LVDS not only reduces the effects of common-mode noise, it also results in a reduced amount of noise emission. When the two adjacent lines of a differential pair transmit data, current flows in equal and opposite directions, creating equal and opposite electromagnetic fields that cancel one another. The strength of these fields is proportional to the flow of current through the lines. Thus the lower current flow in an LVDS transmission line produces a weaker electromagnetic field than other technologies.

At first glance it may seem that one of the drawbacks of using LVDS in an application rather than a traditional single-ended data transmission method is that it requires twice as many wires to transmit the same number of channels. In reality, an LVDS application can easily reduce wires between the transmitter and receiver. With the higher data rates available in LVDS, the same amount of data can be transmitted serially across a single channel, avoiding the necessity of transmitting multiple bits in parallel at slower data rates to achieve the same throughput. Multiple channels of slower parallel data can be serialized onto a single high-speed LVDS channel and transmitted from one point to another. At the receiver the data can then be deserialized and separated into the slower parallel channels. The combination of a serializer and deserializer (SerDes) is a common architecture found in many applications today including CameraLINK and PCI Express.

Another major benefit of LVDS is the low power consumption of LVDS devices. The current-mode driver of LVDS provides a constant 3.5 mA of current through the differential pair. The power consumption at the load can be calculated using the power equation, P = I2R, which states that power is equal to electrical current squared times resistance. Given the 3.5 mA of current through the 100 Ω termination resistor, the power equation results in (3.5 mA)2 x 100 Ω = 1.2 mW. In comparison, another differential data transmission technology, RS422, dissipates 90 mW of power at the load. Other differential signaling technologies, such as RS485, ECL, and PECL, also dissipate significantly more power than LVDS.

LVDS Applications

With the above-mentioned benefits in mind, you are probably already using products and devices that benefit from the strengths of an LVDS interface. Many applications in the consumer electronics industry have taken advantage of the benefits of LVDS. You may be reading this page on a flat panel display that uses an LVDS connection to the graphics card. The last time you printed a report, used a digital copier, or spoke on your cell phone there is a good chance that LVDS was used somewhere in the system to transmit data. These applications require high data rates and some are required to adhere to strict FCC/CISPR requirements for EMI. The high data rates and low EMI radiation of LVDS help many applications meet their throughput demands while staying EMI compliant.

Manufacturers of high-performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), such as Analog Devices and Texas Instruments, use LVDS outputs to transmit digital data at high rates to keep up with the increasing demand for faster sampling rates. One key characteristics of an ADC is that it can accurately convert an analog signal to a corresponding digital representation. Noise radiating from a digital output of the converter can reduce the overall accuracy of the converter by introducing errors at the analog front end. At high sample rates, single-ended outputs generate this kind of harmful noise. LVDS outputs are capable of keeping up with the high data rates and keeping noise emission low, thus protecting the performance of the analog front end. Additionally, some manufacturers have reduced the number of wires necessary to transmit the signals from one point to another by serializing the output bits onto an LVDS pair, which further improves accuracy by avoiding skew-related errors that can occur when transmitting data in parallel.

The low noise emission and high noise rejection characteristics of LVDS make it a practical, reliable choice for military and aerospace applications as well. These applications are often located in harsh, noisy environments with extreme temperatures. LVDS interfaces for avionic communications, surveillance, and intelligence can protect the integrity of the transmitted signals in these environments. In addition, widespread adoption of the standard has produced an abundant supply of LVDS components and devices that make it possible to acquire high-quality, low-cost LVDS parts.

One specific example of an application is the use of LVDS in SDR (software-defined radio) devices. The key goal of this project is to develop a communication device that can be rapidly updated and modified by altering the software that defines the system. The technology behind this concept has been embraced in many applications, such as military communications, including JTRS (joint tactical radio system), signal intelligence, smart antennas, and satellite ground stations. Because of its benefits, LVDS is used as a reliable high-data-transfer interface between components in an SDR device.

LVDS in Test Systems

The increase in applications using LVDS has led to a growing need to test LVDS-based applications. One approach to test LVDS devices uses a device with a dedicated FPGA that can be programmed to generate or analyze test patterns for a device under test. Using this approach, a test developer with expertise in programming FPGAs must program the device to generate or acquire the desired test pattern. This approach offers flexibility in that the functionality of the tester can be modified by reprogramming the FPGA to perform the desired operations. However, there are significant challenges with this approach. FPGA designs are typically application specific and require significant investment in correctly using them in the field. Requiring many man-hours to design, develop, test, validate, and implement, an FPGA may not be an efficient use of test engineering resources.

Another approach to designing an LVDS test system is to use a modular instrument solution based on an open standard, multivendor platform such as PXI. With PXI modular instrumentation, you automatically benefit from the low cost, ease of use, and flexibility of PC technology. Recently, the releases of the PXI-6561 and PXI-6562 digital waveform generator/analyzer devices by National Instruments have provided a modular solution for testing LVDS devices. Familiar industry-standard measurement and automation software such as LabVIEW and LabWindows/CVI can be used to control the PXI digital waveform generator/analyzer devices to implement the desired test. Time-saving software tools such as the NI Digital Waveform Editor can be used to edit existing test patterns and create new test patterns as well as view acquired digital waveforms. New waveforms can be created using fill patterns for common test patterns such as pseudorandom bit sequence (PRBS), reducing the amount of time and expertise required to design and program a quality LVDS test system. Furthermore, because these devices share a common Synchronization and Memory Core (SMC) architecture, they can be tightly synchronized with each other, to form a scalable solution in which channel count can be conveniently expanded as necessary.


LVDS has enjoyed widespread adoption across a variety of applications in consumer and military markets. The advantages of high data rates, low power consumption, high noise immunity, and low noise generation continue to make LVDS an attractive solution for many applications. The general nature of the standard will help LVDS applications quickly adapt and scale with innovations in technology, such as improved processes and lower supply voltages. This quick adaptation will help to ensure the longevity of the LVDS solution in the foreseeable future.

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An Overview of LVDS Technology, National Semiconductor, AN-971, July 1998.

LVDS Owner's Manual, National Semiconductor, 3rd Edition, 2004

LVDS Data Outputs for High-Speed Analog-to-Digital Converters, Analog Devices, 2002

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