The Primary Control Loop (PCL) controls the timing of the VeriStand Engine by performing several execution steps.
The PCL can run in Parallel mode or Low Latency mode. The difference between the modes is the timing of model-related steps:
You can use System Explorer to set the execution mode of the PCL.
|Step||Parallel mode||Low latency mode|
|1||Gets inputs from hardware devices in the system definition.|
|2||Reads asynchronous custom device FIFOs from the previous iteration.|
|3||Runs the Read Data from HW case of inline hardware interface custom devices. If you configured hardware scaling, VeriStand applies the scaling after acquiring all hardware inputs.|
|4||Reads previous iteration data from models in the system definition.||—|
|5||Reads data from the previous iteration of the Data Processing Loop.|
|6||Processes system mappings.|
|7||Runs the Execute Model case of inline model interface custom devices.|
|8||Executes steps of running real-time sequences.
VeriStand executes real-time sequences after input operations but before output operations and continues to run every step of the real-time sequence until the sequence is complete, reaches a Yield step, or completes an iteration of a loop with Auto Yield set to TRUE. If a sequence takes longer than the given time for an iteration of the PCL, the PCL runs late. To avoid errors, break up the timing of the steps by placing Yield steps throughout the sequence and enabling the Auto Yield property for any loops in the sequence.
|9||Processes system mappings.|
|10||Writes data to models.|
|11||Initiates asynchronous execution of models.||Initiates execution of models and waits for them to complete execution.|
|12||—||Reads data from models.|
|13||—||Processes system mappings.|
|14||Writes data to the Data Processing Loop.|
|15||Writes output data to hardware devices.|
|16||Runs the Write Data to HW case of inline hardware interface custom devices.|
|17||Writes data to asynchronous custom device FIFOs.|