Table Of Contents

Primary Control Loop Execution Steps

Last Modified: June 10, 2021

The Primary Control Loop (PCL) controls the timing of the VeriStand Engine by performing several execution steps.

The PCL can run in Parallel mode or Low Latency mode. The difference between the modes is the timing of model-related steps:

  • In Parallel mode, the PCL initiates execution of models and continues to its next iteration without waiting for models to finish executing. This causes a one-cycle delay between when a model executes and when the data it produces is available to the system
  • In Low Latency mode, the PCL waits for the Model Execution Loop(s) to finish writing data to models before it reads and publishes model values to the system. This occurs during every iteration of the system. When the model completes execution, the PCL provides data from the model to other loops during the same iteration that the model generated the data.
    spd-note-note
    Note  

    NI recommends you select Low Latency mode only if you need to minimize the latency between your inputs, model execution, and outputs. Waiting for Model Execution Loops to read, execute, and write on each iteration can significantly slow the execution speed of the system.

You can use System Explorer to set the execution mode of the PCL.

The following table compares the execution steps of Parallel and Low Latency Modes.
spd-note-note
Note  

The VeriStand Engine in both modes executes inline custom devices in the order defined in the system definition file.

Step Parallel mode Low latency mode
1 Gets inputs from hardware devices in the system definition.
spd-note-note
Note  

If the system includes an inline hardware interface custom device, the PCL reads DAQ digital lines and counters after the Read Data from HW case of the custom device executes in step 3.

2 Reads asynchronous custom device FIFOs from the previous iteration.
3 Runs the Read Data from HW case of inline hardware interface custom devices. If you configured hardware scaling, VeriStand applies the scaling after acquiring all hardware inputs.
4 Reads previous iteration data from models in the system definition.
spd-note-note
Note  

This step executes on the second and subsequent iterations.

5 Reads data from the previous iteration of the Data Processing Loop.
6 Processes system mappings.
spd-note-note
Note  

VeriStand components (including custom devices) cannot read data from a previous step until the PCL processes system mappings, even if the previous step acquired the data the component needs.

7 Runs the Execute Model case of inline model interface custom devices.
8 Executes steps of running real-time sequences.
spd-note-note
Note  

VeriStand executes real-time sequences after input operations but before output operations and continues to run every step of the real-time sequence until the sequence is complete, reaches a Yield step, or completes an iteration of a loop with Auto Yield set to TRUE. If a sequence takes longer than the given time for an iteration of the PCL, the PCL runs late. To avoid errors, break up the timing of the steps by placing Yield steps throughout the sequence and enabling the Auto Yield property for any loops in the sequence.

9 Processes system mappings.
10 Writes data to models.
11 Initiates asynchronous execution of models. Initiates execution of models and waits for them to complete execution.
12 Reads data from models.
13 Processes system mappings.
14 Writes data to the Data Processing Loop.
15 Writes output data to hardware devices.
16 Runs the Write Data to HW case of inline hardware interface custom devices.
17 Writes data to asynchronous custom device FIFOs.

Recently Viewed Topics