Configure counter input (CI) channel properties to measure pulse specifications.
|Minimum Value||The minimum value you expect to measure before VeriStand performs any scaling or calibration.|
|Maximum Value||The maximum value you expect to measure before VeriStand performs any scaling or calibration.|
|Sample Clock Source||Specifies the name of the source terminal of the sample clock. You can use an internal counter timebase when performing counter measurements or an external timebase.|
|Sample Clock Rate||Specifies in hertz the sampling rate in samples per channel per second. If you use an external source for the sample clock, set this input to the maximum expected rate of that clock.|
|Active Edge||Specifies whether a timebase cycle is from rising edge to rising
edge or from falling edge to falling edge:
Specifies an amount of time to wait for the channel to return valid data. VeriStand considers invalid data to be repeated values, which might occur if the system attempts to read data faster than the Sample Clock Rate property.
When VeriStand reads invalid data, it continues to read from the channel while it counts until the Timeout Value. VeriStand will return values of NaN until the channel returns valid data again.
For device specific information about the default terminals used for counter measurements and generations, refer to Connecting Counter Signals.