Table Of Contents

Customizing an FPGA VI

Last Modified: November 16, 2020

Modify an FPGA VI to match your hardware device.

Before you begin, copy a sample FPGA VI and project and learn about FPGA customization guidelines and defaults.
  1. Open the FPGA VI in LabVIEW.
  2. Add or remove FPGA I/O items depending on the device and the needs of the project.
    By default, the sample FPGA VI only uses the first 40 lines on connectors 1 and 2. You can add more FPGA I/O items to this project if you want to expose addition I/O lines on your target.
    spd-note-note
    Note  

    For FPGA targets with no analog inputs or outputs, you can remove the analog I/O items from the project and the corresponding FPGA I/O Nodes from the FPGA VI.

    Similarly, the default sample FPGA VI defines the digital lines on connector 0 as 8 PWM inputs and 8 PWM outputs. You may need more or fewer PWM channels. You can add other custom I/O not defined in the sample FPGA VI.

  3. Optional: If the FPGA VI displays broken wires to FPGA I/O nodes, update the corresponding I/O nodes with the correct pins available on the target.
  4. Optional: If the number of packets in either the DMA_READ or DMA_WRITE FIFO is greater than 15, update the FIFO size.
    1. In Project Explorer window, right-click a FIFO I/O item and select Properties.
    2. In the FPGA FIFO Properties dialog box under General, change the Number of Elements, and click OK.
  5. Save the FPGA VI.
After customizing the FPGA VI, compile the VI into a bitfile.

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