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Feedback Node (Reverse) (G Dataflow)

Last Modified: January 10, 2020

Stores data from one execution or loop iteration to the next.

This node operates similarly to shift registers in loops. The node stores data when the loop completes an iteration and then sends the stored data to the next loop iteration. The next iteration reads the data, writes a new value to the data, and sends it through the loop again. This process continues until the loop completes execution.

By default, the node stores data from only the previous execution or iteration. However, you can configure the node to store n samples of data by delaying the output of the node for multiple executions or iterations. If you increase Delay to more than one execution or iteration, the node outputs only the initial value until the delay you set is complete. The node then begins to output the stored values in sequential order. The number on the node represents the number of delays you set.


The only difference between Feedback Node (Reverse) and Feedback Node (Forward) is that the input and output terminals are reversed. Even though the input and output terminals are reversed, there is no difference in the flow of data.



The data to be stored and sent to the next execution or iteration.


initial value

The value for the first execution or loop iteration.

Default: 0



The data stored from the previous execution or iteration.

Initializing Multiple Iteration Values

When you set Delay to two or more executions or iterations, you can wire an array to the initial value input to initialize each iteration value. The first element in the array initializes the first iteration value, the second element in the array initializes the second iteration value, and so on.

Resolving Illegal Cycles

You can insert a Feedback Node into the cycle to resolve cycle errors.

Search within the programming environment to access the following installed examples:
  • Feedback Node – Building an Array
  • Feedback Node – Setting a Delay Value

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices (only within an optimized FPGA VI)

Web Server: Not supported in VIs that run in a web application

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