Integrate external FPGA IP into your FPGA application by creating a component-level IP instance and transferring data between
the component-level IP and your FPGA VI.
Before you can add component-level IP (CLIP) to your FPGA application, you need to declare your IP by creating an External
FPGA IP document. Refer to Creating an External FPGA IP Document from IP Source Files
or Creating an External FPGA IP Document from an IP-XACT File
for help declaring IP for use in your FPGA project.
The EIP document declares external FPGA IP for integration into your FPGA application. When you create a CLIP instance, you
map it to an EIP file. As a result, the ports defined by the IP files declared in the EIP document become clock and I/O constants
in the FPGA VI palette. Add these I/O constants to your FPGA VI diagram to create the interface that interacts with the CLIP
when running on the FPGA target. You can create and configure multiple CLIP instances derived from the same EIP file without
affecting other CLIP instances.
In the Application document for your FPGA target, open or add a Resource Collection.
In the Resource Collection, expand the
Component-level IP section, and click
Create New to create a component-level IP instance.
Click the empty
Component-level IP instance to display its settings on the
Component-Level IP declaration, select an EIP file.
The name of the
Component-level IP instance changes to reflect the configuration of the EIP file you select.
Click on the
Component-level IP instance again to display its settings on the
Item tab displays port configurations imported from the EIP file. The menus and signals available for configuration reflect the
configuration of your EIP file. You can override any configurations from the EIP file without overwriting it.
If your IP has generics, configure them for each CLIP instance.
Item tab for a CLIP instance, locate and expand the
Edit the value for a generic by entering any string value in the text box.
The string value must correspond to the generic type. For example, enter a string of
False for a boolean generic.
Clip clock mapping.
Item tab for the selected CLIP instance displays input clocks under the CLIP clock mapping section. You can configure each input
clock as one of the following:
|Defer to target
|| Select this option to map the CLIP clock to a base clock on the FPGA target. You can select the base clock in SystemDesigner:
Click on the Application document for your FPGA target to display configuration settings on the
Resource Association, click on the pull-down menu next to the CLIP clock you want to configure and select a base clock on your FPGA target.
||Select any derived clock that you have created in the Resource Collection.
IO data type and synchronization registers.
This section displays the ports configured as
Enable in the EIP file.
Configure each data signal as required for your application. You can override the settings derived from the EIP file without
overwriting the EIP file.
Each synchronization register adds a delay of a clock cycle before the FPGA IP code receives the value from Read I/O or Write I/O.
If you place the CLIP I/O constant on the diagram of the FPGA VI, configure
Synchronization registers in relation to the top-level clock of your FPGA VI.
If you place the CLIP I/O constant in Clock-Driven Logic, configure
Synchronization registers in relation to the Clock-Driven Loop clock.
Create the interface between the CLIP and an FPGA VI.
Open the FPGA VI or a Clock-Driven Logic document and display the diagram.
to locate the clocks and I/O for your CLIP instance.
Select a clock or I/O and add it to the FPGA VI diagram.
You can place CLIP I/O constants inside or outside Clock-Driven Logic, but you must pay attention to whether the CLIP crosses
clock domains. Use synchronization registers to add a delay of a clock cycle before the FPGA IP receives the value from Read I/O or Write I/O.
Wire the output of a CLIP I/O constant to Read I/O, Write I/O, or Read/Write I/O.
For example, you can wire an output to Read/Write I/O as shown in the image below.
Because the inputs and outputs of CLIP reflect the port configurations you make in the EIP document, your results may not
match the image above.