Table Of Contents
High Throughput Inverse Tangent (2 Input) (Clock-Driven Logic)
Computes the arctangent of one value divided by another value (y/x). The arctangent is in pi radians, which use fewer FPGA resources than radians. To convert this value into radians, divide the result by pi.
x
This input supports only scalar values of the fixed-point data type.
x and y Coercion
If you wire fixed-point data types with different configurations to the inputs, this node uses a shared, signed fixed-point data type to represent the value of both inputs internally. The maximum word length of this internal data type is 64 bits. If the configurations of the inputs result in an internal word length greater than 64 bits, this node rounds off the fractional bits of one input to achieve an internal word length of 64 bits, resulting in a loss of precision. This node rounds off the input that has the most fractional bits.
y
An input to this operation
This input supports only scalar values of the fixed-point data type.
x and y Coercion
If you wire fixed-point data types with different configurations to the inputs, this node uses a shared, signed fixed-point data type to represent the value of both inputs internally. The maximum word length of this internal data type is 64 bits. If the configurations of the inputs result in an internal word length greater than 64 bits, this node rounds off the fractional bits of one input to achieve an internal word length of 64 bits, resulting in a loss of precision. This node rounds off the input that has the most fractional bits.
input valid
Boolean value that describes whether the next data element has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.
| True | The next data element has arrived for processing. |
| False | The next data element has not arrived for processing. |
ready for output
Boolean value that specifies whether downstream nodes are ready for this node to return a new value.
Use Feedback Node to wire this input to the ready for input input of a downstream node. If this input is False during a given cycle, output valid returns False during that cycle.
| True | The downstream node is ready for the next data element. |
| False | The downstream node is not ready for the next data element. |
Default: False
atan2(y,x)
Arctangent of y/x in pi radians, which use fewer FPGA resources than radians. To convert this value into radians, divide atan2(y,x) by pi.
output valid
Boolean value that indicates whether this node computes a result that downstream nodes can use.
Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
| True | Downstream nodes can use the result this node computes. |
| False | This node returns an undefined value that downstream nodes cannot use. |
Input Coercion
If you wire a fixed-point data type to only x or y, this node coerces the unwired input to match the configuration of the wired terminal.
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application