Table Of Contents
AXI4-Stream Subset Converter (Clock-Driven Logic)
Version:
Last Modified: November 4, 2020
Provides the infrastructure to change the AXI4-Stream interface characteristics between an AXI4-Stream master and slave.
On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.
Need License: No
Interface: AXI4-Stream
Where This Node Can Run:
Desktop OS: none
FPGA: All devices
Web Server: Not supported in VIs that run in a web application