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Retrieve Data from DRAM (Clock-Driven Logic)

Last Modified: September 14, 2017

Retrieves data you request with Request Data from DRAM.


reference in

Reference to a DRAM memory item.


ready for output

Boolean value that specifies whether downstream nodes are ready for this node to return a new value.

Use Feedback Node to wire ready for input of a downstream node to ready for output of the current node. If this input is False during a given cycle, output valid returns False during that cycle.

True The downstream node is ready for the next data point.
False The downstream node is not ready for the next data point.

Default: False


reference out

Reference to a DRAM memory item.



The data this node retrieves from the DRAM memory on the FPGA target.


output valid

Boolean value that indicates whether this node computes a result that downstream nodes can use.

Wire this output to input valid of a downstream node to transfer data from the node to the downstream node.

True Downstream nodes can use the result this node computes.
False This node returns an undefined value that downstream nodes cannot use.

This node may return different undefined values when executed in simulation mode versus when executed on hardware.

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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