After you place an Optimized FPGA VI on the diagram of another FPGA VI or a Clock-Driven Logic document, you can estimate the performance and resource usage on the Optimized FPGA VI integration node from the Item tab.
The estimation data returned should be the same as reported from within the Optimized FPGA VI, but there are a few benefits to performing the estimation on the integration node:
- Directive permanence from integration node—Performance directives, such as clock rate and throughput, persist for all calls of the Optimized FPGA VI when you set them from the integration node. This is not true for directives you set within the Optimized FPGA VI.
- Compilation time savings—Even if you estimated resources from within the Optimized FPGA VI, estimating them again from the integration node saves compilation time when you generate a bitfile for the application containing the Optimized FPGA VI. This estimation data is cached, and as long as you haven't changed code in the Optimized FPGA VI between estimation and bitfile generation, the compiler pulls the cached data.
Be aware that if you switch the interface mode on the integration node from standard to element-by-element or vice versa, any existing wires between the Optimized FPGA node and your input and output code break. Standard mode requires array data, and element-by-element mode requires scalar data.