You can use several Clock-Driven Logic troubleshooting tools that the development environment includes to debug Clock-Driven Logic code in your FPGA application.
Testbench VI—Generates sample data and compares the output of the code under test to an expected outcome to determine whether the code functions properly.
Run GCDL Simulation Node—Executes a Clock-Driven Logic document in simulation mode on the diagram of a VI on a computer target. This node is often part of a testbench VI design. The node accepts sample data that the testbench VI generates, executes the code on the diagram of the Clock-Driven Logic document using the sample data, and outputs the result of the Clock-Driven Logic code.
The connector pane of the
Run GCDL Simulation
node matches the connector pane of the Clock-Driven Logic document it represents.
Sampling Probe— Collects data at run time and displays the data in an interactive graph on the
tab after the application pauses or finishes executing.
Sampling probes are only available in a Clock-Driven Logic document or a Clock-Driven Loop. When you add a sampling probe to a wire, it appears on both the
tab displays the most recent value the probe recorded, while the
tab displays each data point recorded during the most recent application execution.