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Complex Multiplier (Clock-Driven Logic)

Last Modified: August 28, 2017

Represents all operands and results as signed two's-complement data. Operand widths and result widths are parameterizable. Operand widths up to 63 bits are supported.

On the Item tab, click Configure Xilinx IP to configure inputs and outputs for this node.

Need License: No

Interface: AXI4-Stream


Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Web Server: Not supported in VIs that run in a web application

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