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Transferring Data between Clock Domains Using Registers

Last Modified: January 11, 2018

Before completing this task, verify that registers are the best data storage and transfer option for your application.

When you need to store a single unit of data per clock cycle and do not require lossless transfer, use one or more local registers to transfer data between clock domains in a VI targeted to an FPGA. Registers consume fewer FPGA resources than FIFOs and do not consume limited block RAM or dynamic RAM resources. However, if you require lossless data transfer, use FIFOs instead of registers.

What to Use

What to Do

Create the following diagram to transfer data between clock domains using registers.

Customize the gray sections for your unique programming goals.

Use a locally scoped register item to share a register between two Clock-Driven Loops in the same FPGA VI.
Share the same register reference across Clock-Driven Loops so that Write Register and Read Register in separate clock domains access the same FPGA resource.
Process the data that you write to the FPGA register you reference in this clock domain.
Place Write Register in the faster of two clock domains to ensure that Read Register reads valid data. Write Register in a faster clock domain overwrites the data in the register many times for each time the slower clock domain reads a data point.
Place Read Register in the slower of two clock domains. Read Register in a slower clock domain will always read valid data but may miss, or drop, many units of data between one valid read and the next. If you need to read every unit of data, transfer data using FIFOs instead of registers.
Perform operations on the most recent unit of data read from the FPGA register you reference in this clock domain.


If Read Register returns unexpected data, verify that Write Register is in a faster clock domain than Read Register.


Search LabVIEW for the following installed examples:

  • Register
  • Multiple Clock Domains

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