Home > Support > NI Product Manuals > LabVIEW Communications System Design Suite 1.0 Manual
LabVIEW Communications System Design Suite 1.0 Manual

Adder Subtracter (Clock-Driven Logic)

Version:

Creates adders, subtracters, and adders/subtracters that operate on signed or unsigned data. In fabric, the module supports inputs ranging from 1 to 256 bits wide, and outputs ranging from 1 to 258 bits wide. I/O widths are family dependent for DSP48 implementations.

Need License: No

connector_pane_image

Installed By: LabVIEW Communications System Design Suite (introduced in 1.0)

Where This Node Can Run:

Desktop OS: none

FPGA: All devices

Recently Viewed Topics