High Throughput Reciprocal

Specifies the encodings, word lengths, and integer word lengths of the input and output terminals of this function. The configurations you specify determine the value range of the terminals.

• x Type—

  Specifies the fixed-point configuration of the x input terminal.

  If you wire a fixed-point data type to this terminal, LabVIEW dims this section and uses information from the wire.

  • Word length—Specifies the word length of this terminal.
  • Integer word length—Specifies the integer word length of this terminal.
  • Signed—Specifies that this terminal is signed.
  • Unsigned—Specifies that this terminal is unsigned.
• 1/x Type—

  Specifies the fixed-point configuration of the 1/x output terminal.

  • Include overflow status—Specifies whether the output terminal includes the overflow status. LabVIEW propagates this status to downstream nodes. Including this status requires additional FPGA resources. By default, this checkbox does not contain a checkmark.

    If you place a checkmark in this checkbox, the overflow status becomes TRUE in either of the following situations:

    • The overflow status of an input terminal is TRUE.
    • Overflow occurs during the operation of this function.

    If you place a checkmark in the Adapt to source checkbox, LabVIEW sets Include overflow status depending on whether an input terminal includes this status.

  • Word length—Specifies the word length of this terminal.
  • Signed—Specifies that this terminal is signed. LabVIEW matches the encoding you specify in the x Type section and dims this option.
  • Unsigned—Specifies that this terminal is unsigned. LabVIEW matches the encoding you specify in the x Type section and dims this option.
  • Integer word length—Specifies the integer word length of this terminal.
  • Adapt to source—Specifies whether LabVIEW automatically adjusts the fixed-point configuration of the output data type to avoid overflow for nonzero values of x. By default, this checkbox contains a checkmark and LabVIEW dims the following options.
    Note Because the precision of the square root might be infinite, rounding errors always occur.
• Overflow mode—

  Specifies how this function handles overflow. You can choose from the following options:

  • Saturate (default)—Specifies that if overflow occurs, this function saturates the 1/x output terminal.
  • Undefined result—Specifies that if overflow occurs, the value of the 1/x output terminal is undefined.
  Note The Undefined result option does not require any additional FPGA resources. Conversely, the Saturate option requires additional FPGA resources and a longer combinatorial path, which might decrease the maximum clock rate at which this function can compile.

Specifies how this function executes.

• Outside single-cycle Timed Loop—

  Configures this Express VI to execute outside a single-cycle Timed Loop.

  If you select this option and place this Express VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

• Inside single-cycle Timed Loop—

  Configures this Express VI to execute inside a single-cycle Timed Loop.

  If you select this option and place this Express VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

• Throughput—

  Specifies the minimum number of cycles between two successive values of valid input data. Entering a low value in this control results in a high throughput rate. The maximum value of Throughput depends on the Word length of the output terminal. This option is available only if you select Inside single-cycle Timed Loop.

  If you select Outside single-cycle Timed Loop, this function returns a valid result on every call to the function. Therefore, the Throughput control displays 1 call / sample. The Configuration Feedback indicator displays the number of clock cycles this function takes to return a valid result.

Specifies whether to add internal registers for function inputs and/or outputs. These registers will be placed outside of any embedded resources, such as block multipliers or DSP48E slices. This section is available only if you select Inside single-cycle Timed Loop.

• Register inputs—Adds internal registers after the inputs to this function. Selecting this option increases the latency of the function by one cycle.
• Register outputs—Adds internal registers before the outputs of this function. Selecting this option increases the latency of the function by one cycle.

Specifies a setting for displaying an optional block diagram terminal.

• Operation overflow—Specifies that this function displays the operation overflow output terminal on the block diagram. This terminal indicates whether overflow occurred during the operation of this function.

Displays information about how this function executes. This information is based on the configuration options you specify.

x —

Specifies the input to this function. If the value of x is 0, overflow occurs in the 1/x output terminal.

input valid —

Specifies whether the next data point has arrived for processing. Wire output valid of an upstream node to input valid to transfer data from the upstream node to this Express VI.

To display this handshaking terminal, select Inside single-cycle Timed Loop in the configuration dialog box.

ready for output —

Specifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire ready for input of a downstream node to ready for output of the current node.

Note If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle.

To display ready for output, select Inside single-cycle Timed Loop in the configuration dialog box.

1/x —

Returns 1/x.

operation overflow —

Returns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode option determines the value this function returns.

LabVIEW displays the operation overflow terminal only if you place a checkmark in the Operation overflow checkbox. This checkbox is located in the Optional Terminal section of the configuration dialog box.

output valid —

Returns TRUE if this Express VI has computed a result that downstream nodes can use. Use output valid for handshaking with other FPGA VIs and functions.

To display output valid, select Inside single-cycle Timed Loop in the configuration dialog box.

ready for input —

Returns TRUE if this Express VI is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.

Note If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this Express VI during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.

To display ready for input, select Inside single-cycle Timed Loop in the configuration dialog box.