Base Clock Resources for FlexRIO Modular I/O Controllers

Your FlexRIO with Modular I/O Controller provides several base clock resources that can be used to run a LabVIEW FPGA VI. The 40 MHz onboard clock, the 100 MHz clock, and the 200 MHz clock are generated within the device FPGA using a PLL.

The following base clock resources are available for FlexRIO with Modular I/O Controllers.

40 MHz Onboard Clock

The 40 MHz Onboard Clock is the default clock in your LabVIEW FPGA project. You can use this clock as a top-level clock to run your LabVIEW FPGA VI. The top-level clock on an FPGA target determines the execution time of the individual functions and VIs on the FPGA VI block diagram. If you change the frequency of the top-level clock, you also change the execution speed of functions on the block diagram and the execution rate of the FPGA VI.

100 MHz Clock

You can use the 100 MHz Clock as a source for running your LabVIEW FPGA VI. The 100 MHz Clock is generated from a PLL in the module.

200 MHz Clock

You can use the 200 MHz Clock as a source for running your LabVIEW FPGA VI. The 200 MHz Clock is generated from a PLL in the module.

10 MHz Reference Clock

The device derives its 10 MHz Reference Clock from an internal oscillator. For information about how to configure the 10 MHz Reference Clock, refer to the user manual.

DRAM Clock

The DRAM Clock is a 166 MHz clock that drives the DRAM interface.

MGT Reference Clock

The MGT Reference Clock is a user-selectable clock that drives the multi-gigabit transceiver (MGT) interface. Selectable values are 156.25 MHz and 312.5 MHz.