Analog Output

The following DSA devices and modules support analog output:

  • USB-4431
  • PCI/PXI-4461

Output Distortion

You can minimize output distortion by connecting the outputs to external devices with a high input impedance.

  • USB-4431—Each output channel is rated to drive a minimal load of 1 kΩ.
  • PCI/PXI-4461—Each output channel is rated to drive a minimal load of 600 Ω.

However, you can achieve optimal performance with larger load resistances such as 10 kΩ or 100 kΩ. Refer to the specifications for your product for more information.

Analog Output Channel Configurations

The following table outlines the device support for analog output channel configurations. The term pseudodifferential refers to the 50 Ω resistor between the outer connector shell and chassis ground.

Table 5. Differential and Pseudodifferential Support
Model Differential Support Pseudodifferential Support

USB-4431

PCI/PXI-4461

Note Attach PXI modules and PCI devices to the chassis with screws to provide a reliable ground connection. For PXI modules, tighten the screws at the top and bottom of the front face of the module. For PCI devices, keep the screw that held the PCI slot cover to the computer chassis. Reinsert this screw to securely attach the device. For USB-4431 devices, connect the ground terminal on the back of the USB case to the chassis of the host PC.

Choosing Channel Configurations

If the DUT inputs are floating, use either the pseudodifferential or differential configuration.

If the DUT inputs are grounded or ground referenced, use the differential configuration. Using the pseudodifferential output configuration on a grounded DUT creates more than one ground-reference point. This condition may allow ground loop currents which can introduce errors or noise into the measurement. The 50 Ω or 1 kΩ resistor between the negative input and ground is usually sufficient to reduce these errors to negligible levels, but results can vary depending on your system setup.

Configure the channels based on the signal source reference or DUT configuration. Refer to the following table to determine how to configure the channel.

Table 6. DUT Input Reference and Channel Configuration
DUT Input Reference Channel Configuration
Floating Differential or pseudodifferential
Grounded Pseudodifferential

The PCI/PXI-4461 is automatically configured for differential mode when powered on or powered off. This configuration protects the 50 Ω resistor on the negative pin.

Output Impedance

USB-4431 Output Impedance

The differential output impedance between positive and negative signal legs is approximately 50 Ω. There is no high impedance idle output channel configuration for the USB-4431. However the output can be configured to maintain its existing value when idle or return to zero when idle.

PCI/PXI-4461 Output Impedance

The differential output impedance between positive and negative signal legs is approximately 22 Ω when you generate a waveform. When you are not generating a waveform, configure the AO.IdleOutputBehavior property for one of the idle behavior options listed in the following table.

Table 7. Output Impedance
Idle Behavior Option Output Impedance (Differential Mode Only)
Maintain Existing Value 22 Ω
Zero Volts 22 Ω
High Impedance 9 kΩ

DAC

The delta-sigma DACs on the USB-4431 and PCI/PXI-4461 function in a way analogous to delta-sigma ADCs. The digital data first passes through a digital interpolation filter, then to the DAC resampling filter, and finally to the delta-sigma modulator.

In the DAC, the delta-sigma modulator converts high-resolution digital data to high-rate, 1-bit digital data. As in the ADC, the modulator frequency shapes the quantization noise so that almost all of the quantization noise energy is above the Nyquist frequency.

The digital 1-bit data is then passed to an inherently linear 1-bit DAC. The output of the DAC includes quantization noise at higher frequencies, and some images still remain near multiples of eight times the effective sample rate.

Analog Output Filters

Anti-Imaging and Interpolation Filters

A sampled signal repeats itself throughout the frequency spectrum, as shown in the following figure. This figure shows how the signal repetitions begin above one-half the sample rate, fs, and, theoretically, continue up through the spectrum to infinity. Images remain in the sampled data because the data actually represents only the frequency components below one-half fs (the baseband). The device filters out the extra images in the signal in three stages.

Figure 2. Sampled Signal

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First, the data is digitally interpolated by a factor of 2n, where n is a positive integer from 0 to 6 (USB-4431) or 0 to 7 (PCI/PXI-4461). Therefore, the effective sample rate (fes) is 2n × fs. The interpolation factor must be sufficient to move the effective sample rate into the 51.2 kS/s or higher range (USB-4431) or the 102.4 kS/s or higher range (PCI/PXI-4461). The following figure shows an example of four-times interpolation and the resulting images. A linear-phase digital filter then removes almost all energy above one-half fs.

Figure 3. Signal After Digital Filter

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Second, the DAC resamples the data to a new frequency (fDAC). The frequency fDAC is eight times higher than fes. The following figure shows the resulting images.

Figure 4. Images After DAC Filter

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Some further (inherent) filtering occurs at the DAC because the data is digitally sampled and held at eight times fes. This filtering has a sin x/x response, yielding nulls at multiples of eight times fs, as shown in the following figure.

Figure 5. Signal After DAC

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Third, a multi-pole analog filter with a fixed cut-off at 89 kHz (USB-4431) or 243 kHz (PCI/PXI-4461) filters the remaining images, as shown in the following figure.

Figure 6. Signal After Analog Filters

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Filter Delay

Output filter delay—the time required for digital data to propagate through the DAC and interpolation digital filters—varies depending on the update rate for DACs. For example, the filter delay at 10 kS/s for the PCI/PXI-4461 is 38.5 update clock cycles. This signal experiences a delay equal to 3.85 ms. This delay is an important factor for stimulus-response measurements, control applications, or any application where loop time is critical. You often might want to maximize the sample rate to minimize the time required for a specific number of update clock cycles to elapse, since it varies with frequency, as shown in the following tables.

The interpolation filter adds additional output filter delay depending on the update rate. The following tables provide more information about how the interpolation filter affects the output filter delay.

Table 8. USB-4431 Interpolation Factor and Output Filter Delay
Update Rate (kS/s) Interpolation Factor Output Filter Delay (Samples)
0.8 ≤ fs < 1.6 64 63.3
1.6 ≤ fs < 3.2 32 62.6
3.2 ≤ fs < 6.4 16 61.3
6.4 ≤ fs < 12.8 8 58.5
12.8 ≤ fs < 25.6 4 53
25.6 ≤ fs < 51.2 2 42
51.2 ≤ fs ≤ 102.4 1 20
Table 9. PCI/PXI-4461 Interpolation Factor and Output Filter Delay
Update Rate (kS/s) Interpolation Factor Output Filter Delay (Samples)
1.0 ≤ fs ≤ 1.6 128 36.6
1.6 < fs ≤ 3.2 64 36.8
3.2 < fs ≤ 6.4 32 37.4
6.4 < fs ≤ 12.8 16 38.5
12.8 < fs ≤ 25.6 8 40.8
25.6 < fs ≤ 51.2 4 43.2
51.2 < fs ≤ 102.4 2 48.0
102.4 < fs≤ 204.8 1 32.0

FIFO and PCI Data Transfer

DSA device and module input channels share a FIFO buffer, and the output channels share a separate FIFO buffer. The specifications for your device contain information about the buffer sample depth.

The DSA devices and modules have a flexible data transfer request condition. You can program the device to request DMA transfers according to a programmable FIFO condition. Refer to the NI-DAQmx Help or the LabVIEW Help for information about conditions available for specific devices.

Note (USB-4431) USB devices do not allow setting the transfer request condition.

Power Off and Power Loss

(PCI/PXI-4461 ) When the PCI/PXI-4461 is powered off or loses power, the output channels assume a high-impedance state. The outputs of the PCI/PXI-4461 drop to 0.0 V in approximately 8 ms. The following figure illustrates the typical behavior of an PCI/PXI-4461 generating 10 V when powered off or when the device loses power.

Figure 7. PCI/PXI-4461 Power Off and Power Loss Behavior

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