FIFO Overview

The FIFO instrument design library is a wrapper around the LabVIEW FPGA FIFO function.

This wrapper allows you to read and write to the FIFOs while providing handshaking signals to help regulate the flow of data. FIFOs are a key component used in moving data across clock domains. The handshaking signals indicate the readiness of the FIFO to accept data on any particular clock cycle and allow you to control when data is read from the FIFO. This instrument design library contains FPGA VIs.

Handshaking

The handshaking signals are useful when logic executes at different rates on each side of the FIFO.

For example, in pipelined FPGA applications where FIFOs in the pipeline transfer data from one clock domain to another, handshaking signals can perform the following functions:

  • If the data is being written to the FIFO and the FIFO is full, handshaking can send notification that the FIFO cannot accept more data on the current clock cycle, and can hold off the earlier pipeline stages and stop sending data to the FIFO.
  • If the logic that follows the reading of the FIFO is not ready to process new data from the FIFO, handshaking can stop data from being read from the FIFO.
Note The data inside the FIFO can only be cleared using the LabVIEW FPGA FIFO Clear Method.

Refer to the LabVIEW context help of the FIFO VIs for more detailed information about the library interface.