Reports the status of reading I/O data from the I/O items.


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Inputs/Outputs

  • cerrcodeclst.png error in —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

  • FPGA I/O In —

    FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.

  • ierrcodeclst.png error out —

    error out contains error information. This output provides standard error out functionality.

  • FPGA I/O Out —

    FPGA I/O Out returns the FPGA I/O In.

  • ipoly.png Overwrite —

    Overwrite returns TRUE if the Generate I/O Sample Pulse Method function wrote over data for any I/O item before the Read I/O Method function could read it.

    A value of TRUE indicates that the Generate I/O Sample Pulse Method function providing the timing for the I/O item executed at least two times since the last execution of the Read I/O Method function. The Get I/O Read Status Method function does not report the number of data points overwritten, only that some data was overwritten. The value of Overwrite does not reset until this function reads it or the Reset I/O Method function executes.

  • ipoly.png Sample Gated —

    Sample Gated returns TRUE when the Generate I/O Sample Pulse Method function generates a sample pulse that is gated. This function does not report the number of sample pulses gated, only that at least one pulse has been gated since the last time this function executed. The value of Clock Gated does not reset until this function reads it or the Reset I/O Method function executes.

    A sample pulse can be gated for the following reasons:

    • The Generate I/O Sample Pulse Method function tries to execute more quickly than the maximum specified rate of the I/O item.
    • Arbitration for the resource is occurring.
    • The target is conducting an operation such that it cannot issue a clock pulse.

    • To select a method, first configure the node with an I/O item.

    Note Not all targets support the User-Controlled I/O Sampling functions.

    Single-Cycle Timed Loop Details

    This node is supported inside and outside the single-cycle Timed Loop if the target supports it.

    Error Handling Details

    You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.