Initiates a pulse on the sample clock terminal of the I/O items.


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Inputs/Outputs

  • cerrcodeclst.png error in —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

  • FPGA I/O In —

    FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.

  • ierrcodeclst.png error out —

    error out contains error information. This output provides standard error out functionality.

  • FPGA I/O Out —

    FPGA I/O Out returns the FPGA I/O In.

    • To select a method, first configure the node with an I/O item.

    Note Not all targets support the User-Controlled I/O Sampling functions.

    The action that occurs when a sample pulse is generated is hardware-specific and may vary from target to target. For instance, the sample pulse for a multiplexed hardware module will cause a single conversion on a single channel. The same sample pulse on a simultaneous sampling hardware module may cause a conversion to occur on all channels of the module.

    If the node contains multiple I/O items, a sample pulse occurs only if each I/O item is ready to receive the sample pulse. Otherwise, the sample pulse is gated, and the node immediately returns control. Use the Get I/O Read Status Method function, Get I/O Write Status Method function, or the Get I/O Configuration Status Method function to determine whether the sample pulse was gated or generated successfully.

    Single-Cycle Timed Loop Details

    This node is supported inside and outside the single-cycle Timed Loop if the target supports it.

    Error Handling Details

    You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.