Reports the status of writing channel configuration data to I/O items.


icon

Inputs/Outputs

  • cerrcodeclst.png error in —

    error in describes error conditions that occur before this node runs. This input provides standard error in functionality.

  • FPGA I/O In —

    FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.

  • ierrcodeclst.png error out —

    error out contains error information. This output provides standard error out functionality.

  • FPGA I/O Out —

    FPGA I/O Out returns the FPGA I/O In.

  • ipoly.png Data Regenerated —

    Data Regenerated returns TRUE if the Configure I/O Method function regenerates data. A value of TRUE also indicates that the Generate I/O Sample Pulse Method function providing timing for the I/O item executed at least two times since the last execution of the Configure I/O Method function.

    This function does not report the number of data points regenerated, only that some data was regenerated. The value of Data Regen does not reset until read through this function or the Reset I/O Method function executes.

  • ipoly.png Primed —

    Primed returns TRUE when the configuration data path for the I/O item is primed. You must write one or more data values using the Configure I/O Method function to prime the data path before executing the Generate I/O Sample Pulse Method function. Otherwise, the sample pulse is gated. The value of Primed remains TRUE until the Reset I/O Method function executes.

    • To select a method, first configure the node with an I/O item.

    Note Not all targets support the User-Controlled I/O Sampling functions.

    Single-Cycle Timed Loop Details

    This node is supported inside and outside the single-cycle Timed Loop if the target supports it.

    Error Handling Details

    You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.