High Throughput To Fixed-Point

Specifies the encodings, word lengths, and integer word lengths of the input and output terminals of this function. The configurations you specify determine the value range of the terminals.

• x Type—

  Specifies the fixed-point configuration of the x input terminal.

  If you wire a fixed-point data type to this terminal, LabVIEW dims this section and uses information from the wire.

  • Signed—Specifies that this terminal is signed.
  • Unsigned—Specifies that this terminal is unsigned.
  • Word length—Specifies the word length of this terminal.
  • Integer word length—Specifies the integer word length of this terminal.
• y Type—

  Specifies the fixed-point configuration of the y input terminal.

  • Signed—Specifies that this terminal is signed.
  • Unsigned—Specifies that this terminal is unsigned.
  • Word length—Specifies the word length of this terminal.
  • Integer word length—Specifies the integer word length of this terminal.
• Overflow mode—

  Specifies how this function handles overflow. You can choose either Wrap (default) or Saturate.

  Note The Saturateoption requires more FPGA resources and a longer combinatorial path than the Wrap option does. In this situation, choosing Saturate might decrease the maximum clock rate at which this function can compile.
• Rounding mode—

  Specifies how this function rounds the output data if rounding is necessary. You can choose Truncate (default), Round Half-Up, or Round Half-Even. If rounding occurs, the option you choose might affect the amount of resources this function requires.

• Outside single-cycle Timed Loop—Configures this Express VI to execute outside a single-cycle Timed Loop.

  If you select this option and place this Express VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

• Inside single-cycle Timed Loop—Configures this Express VI to execute inside a single-cycle Timed Loop.

  If you select this option and place this Express VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.

• Throughput—Displays the number of cycles between two successive values of valid input data. This number always is one cycle. Therefore, LabVIEW sets the value according to where you place this Express VI.

  If you select Inside single-cycle Timed Loop,LabVIEW sets the throughput to 1 cycle / sample.If you select Outside single-cycle Timed Loop,LabVIEW sets the throughput to 1 call / sample.

• Register outputs—Adds internal registers before the outputs of this function. Selecting this option increases the latency of the function by one cycle.

• Operation overflow—Specifies that this function displays the operation overflow output terminal on the block diagram. This terminal indicates whether overflow occurred during the operation of this function.

x —

Specifies the fixed-point number whose configuration you want to modify.

input valid —

Specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input valid to transfer data from the upstream node to this node.

To display this handshaking terminal, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.

ready for output —

Specifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input of a downstream node to ready for output of the current node.

Note If ready for output is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

To displayready for output, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.

y —

Returns xwith the specified fixed-point configuration applied.

operation overflow —

Returns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode option determines the value this function returns.

LabVIEW displays the operation overflow terminal only if you place a checkmark in the Operation overflow checkbox. This checkbox is located in the Optional Terminal section of the configuration dialog box.

output valid —

Returns TRUE if this node has computed a result that downstream nodes can use. Use output valid for handshaking with other FPGA VIs and functions.

To display this terminal, select the Inside single-cycle Timed Loop in the configuration dialog box.

ready for input —

Returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.

Note If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle.

To display ready for input, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.