Table 2. Commands Table
Command Command Options Description Example
-v, --verbose Increases output logging verbosity.
create-config Creates a configuration template file for the specified NI FPGA. You can use this file to map model ports to a Board I/O.

You can pass on the configuration file as an option for the build-bitfile command.

 
ip2fpgaCLI.exe create-config -p "C:
\Users\SampleUser\Desktop\Sample\SubSystem.slx" -t
"PXIe-7867R" -l 2019 -o "C:\Users\
SampleUser\Desktop\Sample\SubSystem.JSON"
-p, --project=<value> Specifies a path to a Simulink (.slx) project. Simulink must successfully generate HDL code before using this command.
-t, --target=<value> Specifies the NI FPGA target type to generate the bitfile.
-l, --lvversion=<value>(optional) Specifies the LabVIEW version used to compile the bitfile. If not specified, the default is the latest LabVIEW version.
-o, --output=<value> Specifies the path for saving the configuration (.json) file.
build-bitfile Builds a bitfile from the provided SLX file and targeting the specified NI FPGA Board. 
ip2fpgaCLI.exe build-bitfile -p "C:
\Users\SampleUser\Desktop\Sample\SubSystem.slx" -t
"PXIe-7867R" -l 2019 -c "C:\Users\SampleUser
\Desktop\Sample\SubSystem.JSON"
-p, --project=<value> Specifies a path to a SLX file. Simulink must successfully generate HDL code before using this command.
-t, --target=<value> Specifies the NI FPGA target type to generate the bitfile.
-l, --lvversion=<value>(optional) Specifies the LabVIEW version used to compile the bitfile. If not specified, the default is the latest LabVIEW version.
-n, --nocompile (optional) If present, execution stops after generating the LabVIEW FPGA project. No bitfile is compiled.

For more information on this command, refer to Advanced Modifications.
-c, --configfile=<value> (optional) Specifies the path to a Configuration file (.json). If not specified, the default is to map model ports to board I/Os.
generate-lvproj Generates a LabVIEW FPGA Project (.lvproj) for the specified FPGA board from the provided Simulink model (.slx) or .nihdlwprj file. 
ip2fpgaCLI.exe generate-lvproj  -p "C:
\Users\SampleUser\Desktop\Sample\SubSystem.slx" -t
"PXIe-7867R" -l 2019 -c "C:\Users\
SampleUser\Desktop\Sample\SubSystem.JSON"
-p, --project=<value> Specifies a path to a Simulink model (.slx) or .nihdlwprj file. As a prerequisite, Simulink must successfully generate HDL code.
-t, --target=<value> Specifies the NI FPGA target type to generate the bitfile.
-l, --lvversion=<value>(optional) Specifies the LabVIEW version used to compile the bitfile. If not specified, the default is the latest LabVIEW version.
-c, --configfile=<value> (optional) Specifies the path to an FPGA Board IO Configuration file (.JSON).
compile-lvproj Builds a bitfile from the provided LabVIEW FPGA project file (.lvproj). 
ip2fpgaCLI.exe compile-lvproj -p "C:
\Users\SampleUser\Desktop\Sample\PXIe-7867R.lvproj"
-l 2019
-p, --project=<value> Specifies the path to a LabVIEW FPGA project file (.lvproj).
-l, --lvversion=<value> (optional) Specifies the LabVIEW version used to compile the bitfile. If not specified, the default is the latest LabVIEW version.
create-template Creates a template you can modify for later use as a reference design project. 
ip2fpgaCLI.exe create-template –t PXIe-7971R -o "C:\Users\SampleUser\Desktop\RefDesign"
-t, --target=<value> Specifies the NI FPGA target type to create the template project for.
-l, --lvversion=<value> (optional) Specifies the LabVIEW version used to compile the bitfile. If not specified, the default is the latest LabVIEW version.
-o, --outputdir=<value> Specifies the template LabVIEW project location.
Note Use NI FPGA Bitfile Generation Workflow in the HDL Coder Workflow advisor to generate the .nihdlwprj file. HDL Coder Support Package for NI FPGA Hardware must be installed to use this workflow. Execute the Generate Project step to create the .nihdlwprj file. The file will be in hdl_prj\ip2fpgacli.