This section provides steps for creating socketed CLIP for use with your application. Socketed CLIP provides the following functionality:

  • Allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI.
  • Allows the CLIP to communicate directly with circuitry external to the FPGA.
  • Allows your IP to communicate directly with both the FPGA VI and the external FPGA module connector interface.

    You can develop socketed CLIP either by using the Xilinx Vivado tools, or by exporting a LabVIEW FPGA VI as a Vivado Design Suite project.

  • The Xilinx Vivado tools create a blank project, from which you can develop socketed CLIP. For more information about using the Xilinx Vivado tools to develop socketed CLIP, refer to the Accessing the Xilinx Vivado Tools section.
  • You can also design your project in LabVIEW, then export the project to the Vivado Design Suite. For more information about exporting a LabVIEW FPGA VI as a Vivado Design Suite project, refer to the Exporting to Vivado section.