The following chapter contains information about the PXIe-6591R clocking architecture.

The PXIe-6591R is a high-speed serial interfacing module. The PXIe-6591R hardware architecture allows you to fully customize your serial digital protocol application. The high-speed serial interface uses Xilinx GTX transceiver technology; you can reuse existing protocol IP that works with Xilinx GTX transceivers, or you can develop your own protocol IP. If you develop your own protocol IP, the IP must be developed for a Xilinx Kintex-7 GTX transceiver.

Note The PXIe-6591R hardware does not require calibration. PXIe-6591R-based projects consist of the following key components:
  • PXIe-6591R front panel connectors for data, clocking, and triggering external to the module
  • Socketed CLIP for HDL IP and interface definition from the FPGA VI to the PXIe-6591R front panel
  • Xilinx Kintex-7 FPGA
  • Dynamic random access memory (DRAM)
  • NI-defined bus interface from the FPGA to the host PC

    The following figure illustrates the key components of the PXIe-6591R architecture.

    Figure 1. PXIe-6591R System Architecture Elements