Exporting a LabVIEW FPGA VI as a Vivado project allows you to design the exported project in LabVIEW, then compile it into a bitfile in the Vivado Design Suite. You can then run the bitfile on an FPGA target in the FPGA Module. This option takes advantage of the design features provided by the Vivado Design Suite while making full use of LabVIEW FPGA hardware resources. Refer to the Exporting FPGA VIs as Vivado Design Suite Projects (FPGA Module) topic in the LabVIEW Help for more information about this feature.

The PXIe-6591R, PXIe-6592R, and PXIe-7902 devices support exporting to Vivado. The Aurora sample projects for the PXIe-6591R, PXIe-6592R, and PXIe-7902R provide out-of-the-box support that demonstrates how to use hardware design files as an entry point when exporting to Vivado.

Complete the following steps to export a LabVIEW FPGA VI as a Vivado Design Suite project.

  1. Open the Aurora Simple Streaming sample project for your hardware device. The following image shows the PXIe-6592R Aurora Simple Streaming sample project as an example. The files with the UserRTL_ prefix are used as the entry point when the top-level FPGA VI is exported to Vivado.
  2. In the LabVIEW project, select the Stream Controller [device name] build specification under the Build Specifications item.
  3. Navigate to the LabVIEW project root directory. The exported project is located inside the ProjectExportForVivado folder. The exported project contains encrypted LabVIEW FPGA files, the unencrypted design files with the UserRTL_ prefix, and the Vivado project files.
  4. Open the Vivado project using the LaunchVivadoDesignSuite.bat file.
  5. The source hierarchy loads once Vivado launches.
    Note The hierarchy source is encrypted, except for the design files prefixed with UserRTL_ and added to the FPGA target as a socketed CLIP.
  6. Navigate to the UserRTL_ files in the hierarchy.
  7. Use the unencrypted design files as an entry point for IP you are developing in Vivado. You can compile the design from Vivado to generate a LabVIEW bitfile (.lvbitx) that can be loaded on the respective NI targets.