Complete the following steps to run Xilinx Vivado and generate a blank project for CLIP development.

  1. Ensure that your system meets the system requirements listed in the NI High-Speed Serial Instruments Readme, available from the Start menu and at ni.com/manuals. You can check the versions of the tool on your machine by selecting Start » Control Panel » 
Programs and Features.
    Note If Vivado is installed by LabVIEW FPGA, it does not appear in Programs and Features.
  2. Open the Xilinx Vivado Tool directory by navigating to C:\NIFPGA\programs\
VivadoXXXX_Y, where XXXX and Y refer to the Xilinx Vivado tool versions. For example, <VIVADO_DIR> version 2013.4 is located at C:\NIFPGA\programs\
Vivado2013_4.
  3. Run the Xilinx Vivado batch file: <XilinxVivadoDir>\bin\vivado.bat.

    You may receive the following warning when launching Vivado.

    Figure 16. EDK Environment Error Message

    This error message is expected. You can ignore the error message if you are not using the Xilinx Embedded Development Kit (EDK). The EDK is not required for development with the high-speed serial device.

  4. Click New Project and follow the instructions in the wizard.

    You can also export an FPGA VI as a Vivado Design Suite project, as detailed in the Exporting to Vivado section.