Optimizing Third-Party IP for LabVIEW Integration

When Generating an IP Core from the Xilinx Vivado IP Catalog

Refer to Generating and Integrating Aurora IP into Your LabVIEW Project, available by search at ni.com, for a step-by-step procedure you can use as guidance for generating any IP core from the Xilinx Vivado IP Catalog.
Ensure you have purchased and installed all necessary licenses. For more information about managing licenses, search for UG 973: Vivado Design Suite: Release Notes, Installation, and Licensing at www.xilinx.com.
In the IP core settings, select AXI4-Stream for high-speed data streams.
NI does not guarantee compatibility between AXI4-Lite for DRP accesses in the Xilinx IP cores and LabVIEW FPGA AXI4-Lite adapters. Refer to the Aurora Streaming example projects in the FlexRIO Integrated I/O Project Creator for an example of how to use the LabVIEW FPGA AXI4-Lite adapters to connect to DRP within the CLIP.

When Using Existing VHDL IP inside CLIP or IPIN

For instructions on importing existing IP into your project, refer to Importing External IP Into LabVIEW FPGA available by search at ni.com.
CLIP does not support custom user libraries in the VHDL. If your VHDL uses custom user libraries, you can either reference the default reference library instead of a custom user library, or create a netlist from the VHDL and integrate the netlist using CLIP.
Refer to the Creating or Acquiring IP topic in the LabVIEW FPGA Module Help for more information about using existing VHDL IP inside CLIP or IPIN.

When Modifying Third-Party IP Core Logic

If you purchase or license an IP core from Xilinx, refer the Xilinx Product Guide for the IP before attempting to make any modifications.
Ensure all clocks are connected.
Ensure AXI4-Lite management signals are connected correctly to the DRP signals on the MGT primitives corresponding to your FPGA type.
When designing in Vivado, you can access resources outside of the IP core logic, such as MGT_RefClk input buffers and QPLL wrappers, by selecting Include Shared Logic in example design in the IP wizard.

How to Use Vivado's Including Shared Logic Options

The IP wizard inside Vivado provides options for including shared logic in the VHDL.

The following diagrams compare how the IBUFDS_GTE3/4 resource is exposed in the top-level CLIP VHDL when selecting Including Shared Logic in example design or Including Shared Logic in core.

To access resources outside the IP core logic, select the Include Shared Logic in example design option.

Including Shared Logic in core Option

Including Shared Logic in example design Option

When Compiling LabVIEW FPGA VIs that Incorporate Third-Party IP

You may need to purchase and install additional licenses to compile FPGA designs that incorporate licensed cores from Xilinx or third-party IP vendors. Refer to UG 973: Vivado Design Suite: Release Notes, Installation, and Licensing at www.xilinx.com for information about managing licenses.
FlexRIO high-speed serial instruments include large FPGA devices that require a 64-bit compile worker.
You cannot add additional licenses to remote compile workers in the NI LabVIEW FPGA Compile Cloud Service. You cannot use NI LabVIEW FPGA Compile Cloud Service to compile designs that incorporate Xilinx or other third-party licensed cores.

When Writing a VHDL Wrapper around the Protocol IP Core

Keep the interface between the CLIP and the LabVIEW FPGA diagram as simple as possible.
Note LabVIEW stores values in big-endian format, and your IP may accept only little-endian format. For simplicity and ease of use, perform endian conversions in the CLIP and keep them off the LabVIEW diagram.
Do not pass asynchronous signals to the LabVIEW FPGA diagram. Register the signals in a clock domain in the VHDL logic before passing them to the LabVIEW FPGA diagram.
Run synthesis.
Use AXI4-Stream and AXI4-Lite interfaces for streaming data and register accesses. NI provides AXI4-Stream and AXI4-Lite wrappers to use on the LabVIEW FPGA diagram.
If you expose an AXI4-Lite endpoint, use Xilinx AXI4 interconnect IP to expose only one AXI4-Lite endpoint to the LabVIEW FPGA diagram.
Document the frequency of clocks coming from CLIP. In larger applications, the default enable chain in LabVIEW can create routing congestion and limit performance. Consider supporting enable chain removal. Refer to Improving Timing Performance in Large Designs in the LabVIEW FPGA Module Help for more information about how and when to remove enable chains.
Implement a state machine that allows asynchronous resets. If you declare an input signal as a reset signal in the Configure CLIP wizard, then that signal is asserted when the LabVIEW FPGA VI is not running.
Implement a state machine that resets the protocol cores when the PORT# module is absent.
Connect various clocks from your CLIP to the DebugClks std_logic_vector in order to use host-side frequency counter debugging utilities.
Provide timing constraints in the constraints file for your CLIP. Include timing constraints for clocks within your CLIP, but do not include pin or location constraints on MGTs transceiver lanes and RefClks.
Use the TXOUTCLK and RXOUTCLK clock constraints for your high-speed serial CLIP if your protocol uses it directly.
Refer to the following syntax example for a clock constraint:
```
create_clock -period <period in ns> [get_pins %ClipInstancePath%/<path to your clock pin relative to the top level CLIP VHDL>] 
```
If you generate an asynchronous reset within your CLIP VHDL, create a false path constraint from the register that generates the reset signal and include a "don't touch" attribute.
Refer to the following syntax example for a "don't touch" attribute:
```
attribute dont_touch : string; attribute dont_touch of <signal name> : signal is "true";
```
Refer to the following syntax example for a false path constraint:
```
set_false_path -from [get_cells %ClipInstancePath%/<path to your register>]
```
When writing constraints, you may need to refer to the instance name of the CLIP or the absolute path to the CLIP instance in the VHDL hierarchy. Refer to Applying Constraints Using %ClipInstanceName% and %ClipInstancePath% for more information about using the search-and-replace keywords %ClipInstanceName% and %ClipInstancePath%.

When Documenting Your IP

Note the endianness of the CLIP in order to properly interface the CLIP to the LabVIEW FPGA diagram.
Clearly define which portion of the entity faces the diagram and which portion of the entity faces the front panel.
Clearly define LED behavior.
Describe how each signal is used and document unused signals. Signal use can affect which ports are active with the IP and affect the behavior of cables upon insertion and removal.
Use the DebugClks signal to determine the health of the internal clocks being sent to the IP. Define which bits of the 4-bit vector correspond to the clock being monitored.
Document how you integrate AXI4-Lite signals with LabVIEW data types. Some AXI4-Lite signals do not integrate easily with LabVIEW data types. For example, address ports can have widths of 11, but LabVIEW only provides addresses with widths of 8, 16, 32, and 64. Additionally, the AXI4-Lite and AXI4-Stream adapters are configured for use with fixed-point I/O.
Document how the CLIP uses and routes clocks. You must route clocks to the diagram for use with the single-cycle timed loop (SCTL) in LabVIEW FPGA.
Document the address map of individual components within any AXI4-Lite interfaces.

Developing FlexRIO High-Speed Serial Protocols

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