Applying Constraints Using %ClipInstanceName% and %ClipInstancePath%

You can include all CLIP-specific user constraints, except pin placement constraints, in the constraints file (.xdc) you will add to your LabVIEW project.

Complete the following steps to apply constraints on specific components within your CLIP without specifying the location of the component in the VHDL hierarchy.

  1. In a text file, preface your constraints with the following macros: 
    create_clock -period 10.000 -name %ClipInstanceName%Clk -waveform {0.000 5.000} -add [get_pins %ClipInstancePath%/clk]
     set_clock_latency -clock [get_clocks {%ClipInstanceName%CLK}] 10.0 [get_pins {%ClipInstancePath%/cAddOut[0]}]
  2. Save the file as DemoClipAdder.xdc.
  3. Add the DemoClipAdder.xdc constraints file and the VHD file as synthesis files in the Configure CLIP wizard.
    Note When using these macros, you do not need to include a separate constraints file for each CLIP instance because the LabVIEW FPGA Module will create a unique name for each instance.
    Note The Xilinx compilation tools may remove an unused CLIP signal from the bitstream. If you get an NGBuild error during compilation, remove the constraint or use the signal in an FPGA VI.