Customizing High-Speed Serial IP by Exporting to Vivado

Before you begin, you must install the necessary Xilinx compilations tool for Vivado on the local computer to export an FPGA VI as a Vivado Design Suite project or open the exported project.
Note If you choose to implement an Aurora Streaming project without customization, you will not need to export to Vivado Design Suite, and you do not need to install the Xilinx compilation tool for Vivado.
If you do not want to use the Aurora Streaming example project without customization, you will need to design or modify IP using Vivado Design Suite. You can use a LabVIEW FPGA VI as the entry point for customizing IP by exporting your LabVIEW project to Vivado. With this feature, LabVIEW exports unencrypted hardware design files that can be opened in Vivado, customized, and then compiled into a bitfile or loaded into LabVIEW to generate a CLIP. You can then instantiate the CLIP in the I/O socket and run the bitfile on an FPGA target in LabVIEW FPGA.

The Aurora Streaming example projects provide the Stream Controller VI that can be used as an entry point for customizing Aurora IP in Vivado. Complete the following steps to export the Stream Controller VI to Vivado.

Note To implement a design using a different protocol, use the CLIP Template example project instead, and specify the NI6593 Template VI or NI6594 Template VI as the top-level VI.
  1. From the FlexRIO Integrated I/O Project Creator, open the Aurora Streaming example project for your model and FPGA size.
  2. In the LabVIEW Project Explorer window, expand your FPGA target item tree, right-click the Build Specifications item and select New»Project Export for Vivado from the shortcut menu.
  3. On the Information page, specify the destination directory where you want to export the files.
  4. On the Source Files page, specify NI6593 or NI6594 Stream Controller (FPGA).vi as the top-level VI.
  5. Click Build.
    LabVIEW creates the exported project inside a ProjectExportForVivado folder in the destination directory you specified in step 3. The exported project contains encrypted LabVIEW FPGA files, the unencrypted design files with the UserRTL_ prefix, and the Vivado project.
  6. Navigate to the destination directory you specified in step 3 and open the Vivado project using the LaunchVivadoDesignSuite.bat file.
  7. Once Vivado launches, the source hierarchy loads.
  8. Navigate to the UserRTL_ files in the hierarchy.
  9. Use the unencrypted design files (UserRTL_) as an entry point to develop IP in Vivado. When your design is complete, follow the instructions in the Configuring LabVIEW FPGA Targets topic to instantiate your CLIP in the I/O socket. You can also compile the design from Vivado to generate a LabVIEW bitfile (.lvbitx) that can be loaded onto the FPGA target.